Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3765471 [patent_doc_number] => 05802571 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory' [patent_app_type] => 1 [patent_app_number] => 8/734318 [patent_app_country] => US [patent_app_date] => 1996-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2718 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802571.pdf [firstpage_image] =>[orig_patent_app_number] => 734318 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/734318
Apparatus and method for enforcing data coherency in an information handling system having multiple hierarchical levels of cache memory Oct 20, 1996 Issued
Array ( [id] => 4059761 [patent_doc_number] => 05875476 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Filing system for managing recording and retrieving of information' [patent_app_type] => 1 [patent_app_number] => 8/733304 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875476.pdf [firstpage_image] =>[orig_patent_app_number] => 733304 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733304
Filing system for managing recording and retrieving of information Oct 16, 1996 Issued
Array ( [id] => 4259778 [patent_doc_number] => 06092153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Subsettable top level cache' [patent_app_type] => 1 [patent_app_number] => 8/733334 [patent_app_country] => US [patent_app_date] => 1996-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2997 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092153.pdf [firstpage_image] =>[orig_patent_app_number] => 733334 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733334
Subsettable top level cache Oct 16, 1996 Issued
Array ( [id] => 3803159 [patent_doc_number] => 05737573 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer' [patent_app_type] => 1 [patent_app_number] => 8/733721 [patent_app_country] => US [patent_app_date] => 1996-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 14 [patent_no_of_words] => 6795 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737573.pdf [firstpage_image] =>[orig_patent_app_number] => 733721 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/733721
Asynchronous access system having an internal buffer control circuit which invalidates an internal buffer Oct 15, 1996 Issued
Array ( [id] => 4040683 [patent_doc_number] => 05926831 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-20 [patent_title] => 'Methods and apparatus for control of speculative memory accesses' [patent_app_type] => 1 [patent_app_number] => 8/731350 [patent_app_country] => US [patent_app_date] => 1996-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2944 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/926/05926831.pdf [firstpage_image] =>[orig_patent_app_number] => 731350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/731350
Methods and apparatus for control of speculative memory accesses Oct 10, 1996 Issued
Array ( [id] => 4071739 [patent_doc_number] => 05933858 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-03 [patent_title] => 'Efficient internal address encoding scheme for an integrated circuit which facilitates multiple addressing modes' [patent_app_type] => 1 [patent_app_number] => 8/725798 [patent_app_country] => US [patent_app_date] => 1996-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 2889 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/933/05933858.pdf [firstpage_image] =>[orig_patent_app_number] => 725798 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/725798
Efficient internal address encoding scheme for an integrated circuit which facilitates multiple addressing modes Oct 3, 1996 Issued
Array ( [id] => 3997356 [patent_doc_number] => 05911150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Data storage tape back-up for data processing systems using a single driver interface unit' [patent_app_type] => 1 [patent_app_number] => 8/724966 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 6244 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911150.pdf [firstpage_image] =>[orig_patent_app_number] => 724966 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724966
Data storage tape back-up for data processing systems using a single driver interface unit Oct 2, 1996 Issued
Array ( [id] => 3997401 [patent_doc_number] => 05911153 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-08 [patent_title] => 'Memory design which facilitates incremental fetch and store requests off applied base address requests' [patent_app_type] => 1 [patent_app_number] => 8/724878 [patent_app_country] => US [patent_app_date] => 1996-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3010 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/911/05911153.pdf [firstpage_image] =>[orig_patent_app_number] => 724878 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724878
Memory design which facilitates incremental fetch and store requests off applied base address requests Oct 2, 1996 Issued
Array ( [id] => 4020014 [patent_doc_number] => 05860128 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Method and apparatus for sampling data from a memory' [patent_app_type] => 1 [patent_app_number] => 8/724370 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8985 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860128.pdf [firstpage_image] =>[orig_patent_app_number] => 724370 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724370
Method and apparatus for sampling data from a memory Sep 30, 1996 Issued
Array ( [id] => 3960313 [patent_doc_number] => 05930822 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-07-27 [patent_title] => 'Method and system for maintaining strong ordering in a coherent memory system' [patent_app_type] => 1 [patent_app_number] => 8/720330 [patent_app_country] => US [patent_app_date] => 1996-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3444 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/930/05930822.pdf [firstpage_image] =>[orig_patent_app_number] => 720330 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/720330
Method and system for maintaining strong ordering in a coherent memory system Sep 26, 1996 Issued
Array ( [id] => 3662549 [patent_doc_number] => 05684976 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-11-04 [patent_title] => 'Method and system for reduced address tags storage within a directory having a tree-like data structure' [patent_app_type] => 1 [patent_app_number] => 8/717358 [patent_app_country] => US [patent_app_date] => 1996-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3550 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/684/05684976.pdf [firstpage_image] =>[orig_patent_app_number] => 717358 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717358
Method and system for reduced address tags storage within a directory having a tree-like data structure Sep 24, 1996 Issued
Array ( [id] => 3955297 [patent_doc_number] => 05940861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-17 [patent_title] => 'Method and apparatus for preempting operations in a nonvolatile memory in order to read code from the nonvolatile memory' [patent_app_type] => 1 [patent_app_number] => 8/717268 [patent_app_country] => US [patent_app_date] => 1996-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 7395 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/940/05940861.pdf [firstpage_image] =>[orig_patent_app_number] => 717268 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/717268
Method and apparatus for preempting operations in a nonvolatile memory in order to read code from the nonvolatile memory Sep 19, 1996 Issued
Array ( [id] => 4059648 [patent_doc_number] => 05875468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-02-23 [patent_title] => 'Method to pipeline write misses in shared cache multiprocessor systems' [patent_app_type] => 1 [patent_app_number] => 8/708298 [patent_app_country] => US [patent_app_date] => 1996-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 4897 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/875/05875468.pdf [firstpage_image] =>[orig_patent_app_number] => 708298 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/708298
Method to pipeline write misses in shared cache multiprocessor systems Sep 3, 1996 Issued
Array ( [id] => 3674441 [patent_doc_number] => 05657466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Circuit for designating write and read address to provide a delay time in a sound system' [patent_app_type] => 1 [patent_app_number] => 8/703929 [patent_app_country] => US [patent_app_date] => 1996-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 2720 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657466.pdf [firstpage_image] =>[orig_patent_app_number] => 703929 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703929
Circuit for designating write and read address to provide a delay time in a sound system Aug 27, 1996 Issued
Array ( [id] => 4412343 [patent_doc_number] => 06298423 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-02 [patent_title] => 'High performance load/store functional unit and data cache' [patent_app_type] => 1 [patent_app_number] => 8/703299 [patent_app_country] => US [patent_app_date] => 1996-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 29 [patent_no_of_words] => 14324 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/298/06298423.pdf [firstpage_image] =>[orig_patent_app_number] => 703299 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/703299
High performance load/store functional unit and data cache Aug 25, 1996 Issued
Array ( [id] => 3735838 [patent_doc_number] => 05701429 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-23 [patent_title] => 'Method and system for maintaining concurrent data access during device upgrade' [patent_app_type] => 1 [patent_app_number] => 8/698825 [patent_app_country] => US [patent_app_date] => 1996-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 38 [patent_no_of_words] => 4779 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/701/05701429.pdf [firstpage_image] =>[orig_patent_app_number] => 698825 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698825
Method and system for maintaining concurrent data access during device upgrade Aug 15, 1996 Issued
Array ( [id] => 3922825 [patent_doc_number] => 05752264 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'Computer architecture incorporating processor clusters and hierarchical cache memories' [patent_app_type] => 1 [patent_app_number] => 8/698192 [patent_app_country] => US [patent_app_date] => 1996-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 15275 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752264.pdf [firstpage_image] =>[orig_patent_app_number] => 698192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698192
Computer architecture incorporating processor clusters and hierarchical cache memories Aug 14, 1996 Issued
Array ( [id] => 3900942 [patent_doc_number] => 05806082 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-08 [patent_title] => 'Wrap-around mechanism for memory split-wordline read' [patent_app_type] => 1 [patent_app_number] => 8/698055 [patent_app_country] => US [patent_app_date] => 1996-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2970 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/806/05806082.pdf [firstpage_image] =>[orig_patent_app_number] => 698055 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/698055
Wrap-around mechanism for memory split-wordline read Aug 12, 1996 Issued
Array ( [id] => 4206765 [patent_doc_number] => 06131150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-10 [patent_title] => 'Scaled memory allocation system' [patent_app_type] => 1 [patent_app_number] => 8/692649 [patent_app_country] => US [patent_app_date] => 1996-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3085 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/131/06131150.pdf [firstpage_image] =>[orig_patent_app_number] => 692649 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/692649
Scaled memory allocation system Aug 5, 1996 Issued
Array ( [id] => 3700442 [patent_doc_number] => 05696938 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-09 [patent_title] => 'Computer system permitting mulitple write buffer read-arounds and method therefor' [patent_app_type] => 1 [patent_app_number] => 8/690050 [patent_app_country] => US [patent_app_date] => 1996-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 5661 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/696/05696938.pdf [firstpage_image] =>[orig_patent_app_number] => 690050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/690050
Computer system permitting mulitple write buffer read-arounds and method therefor Jul 30, 1996 Issued
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