Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3738475 [patent_doc_number] => 05652861 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-29 [patent_title] => 'System for interleaving memory modules and banks' [patent_app_type] => 1 [patent_app_number] => 8/687692 [patent_app_country] => US [patent_app_date] => 1996-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4968 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/652/05652861.pdf [firstpage_image] =>[orig_patent_app_number] => 687692 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687692
System for interleaving memory modules and banks Jul 25, 1996 Issued
Array ( [id] => 3922803 [patent_doc_number] => 05752262 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-05-12 [patent_title] => 'System and method for enabling and disabling writeback cache' [patent_app_type] => 1 [patent_app_number] => 8/687242 [patent_app_country] => US [patent_app_date] => 1996-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3939 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/752/05752262.pdf [firstpage_image] =>[orig_patent_app_number] => 687242 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/687242
System and method for enabling and disabling writeback cache Jul 24, 1996 Issued
Array ( [id] => 3707691 [patent_doc_number] => 05680572 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-21 [patent_title] => 'Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers' [patent_app_type] => 1 [patent_app_number] => 8/680109 [patent_app_country] => US [patent_app_date] => 1996-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 16 [patent_no_of_words] => 9239 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/680/05680572.pdf [firstpage_image] =>[orig_patent_app_number] => 680109 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/680109
Cache memory system having data and tag arrays and multi-purpose buffer assembly with multiple line buffers Jul 14, 1996 Issued
Array ( [id] => 3901003 [patent_doc_number] => 05897657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-27 [patent_title] => 'Multiprocessing system employing a coherency protocol including a reply count' [patent_app_type] => 1 [patent_app_number] => 8/674314 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 14650 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/897/05897657.pdf [firstpage_image] =>[orig_patent_app_number] => 674314 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/674314
Multiprocessing system employing a coherency protocol including a reply count Jun 30, 1996 Issued
Array ( [id] => 4011489 [patent_doc_number] => 05893150 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-04-06 [patent_title] => 'Efficient allocation of cache memory space in a computer system' [patent_app_type] => 1 [patent_app_number] => 8/675306 [patent_app_country] => US [patent_app_date] => 1996-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3205 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/893/05893150.pdf [firstpage_image] =>[orig_patent_app_number] => 675306 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/675306
Efficient allocation of cache memory space in a computer system Jun 30, 1996 Issued
08/665597 SYSTEM AND METHOD FOR ALLOCATING CACHE MEMORY STORAGE SPACE Jun 17, 1996 Abandoned
Array ( [id] => 3765578 [patent_doc_number] => 05802578 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-01 [patent_title] => 'Multinode computer system with cache for combined tags' [patent_app_type] => 1 [patent_app_number] => 8/662380 [patent_app_country] => US [patent_app_date] => 1996-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5877 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/802/05802578.pdf [firstpage_image] =>[orig_patent_app_number] => 662380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/662380
Multinode computer system with cache for combined tags Jun 11, 1996 Issued
Array ( [id] => 3805683 [patent_doc_number] => 05822760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-13 [patent_title] => 'Cache-memory system having multidimensional cache' [patent_app_type] => 1 [patent_app_number] => 8/659702 [patent_app_country] => US [patent_app_date] => 1996-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 58 [patent_no_of_words] => 13160 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/822/05822760.pdf [firstpage_image] =>[orig_patent_app_number] => 659702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/659702
Cache-memory system having multidimensional cache Jun 9, 1996 Issued
Array ( [id] => 3902741 [patent_doc_number] => 05724550 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-03-03 [patent_title] => 'Using an address pin as a snoop invalidate signal during snoop cycles' [patent_app_type] => 1 [patent_app_number] => 8/658004 [patent_app_country] => US [patent_app_date] => 1996-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10341 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/724/05724550.pdf [firstpage_image] =>[orig_patent_app_number] => 658004 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/658004
Using an address pin as a snoop invalidate signal during snoop cycles Jun 3, 1996 Issued
Array ( [id] => 3816028 [patent_doc_number] => 05829048 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-10-27 [patent_title] => 'Reset propagation for a multi-port storage controller' [patent_app_type] => 1 [patent_app_number] => 8/657340 [patent_app_country] => US [patent_app_date] => 1996-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/829/05829048.pdf [firstpage_image] =>[orig_patent_app_number] => 657340 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/657340
Reset propagation for a multi-port storage controller Jun 2, 1996 Issued
Array ( [id] => 4019988 [patent_doc_number] => 05860127 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Cache memory employing dynamically controlled data array start timing and a microcomputer using the same' [patent_app_type] => 1 [patent_app_number] => 8/653278 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8357 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860127.pdf [firstpage_image] =>[orig_patent_app_number] => 653278 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653278
Cache memory employing dynamically controlled data array start timing and a microcomputer using the same May 23, 1996 Issued
Array ( [id] => 3849831 [patent_doc_number] => 05761478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Programmable memory interface for efficient transfer of different size data' [patent_app_type] => 1 [patent_app_number] => 8/653220 [patent_app_country] => US [patent_app_date] => 1996-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 88 [patent_no_of_words] => 13012 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761478.pdf [firstpage_image] =>[orig_patent_app_number] => 653220 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/653220
Programmable memory interface for efficient transfer of different size data May 23, 1996 Issued
Array ( [id] => 4273640 [patent_doc_number] => 06209071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Asynchronous request/synchronous data dynamic random access memory' [patent_app_type] => 1 [patent_app_number] => 8/648300 [patent_app_country] => US [patent_app_date] => 1996-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 9813 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/209/06209071.pdf [firstpage_image] =>[orig_patent_app_number] => 648300 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/648300
Asynchronous request/synchronous data dynamic random access memory May 6, 1996 Issued
Array ( [id] => 3843412 [patent_doc_number] => 05784700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Memory interface with address shift for different memory types' [patent_app_type] => 1 [patent_app_number] => 8/641820 [patent_app_country] => US [patent_app_date] => 1996-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 52 [patent_figures_cnt] => 88 [patent_no_of_words] => 12972 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784700.pdf [firstpage_image] =>[orig_patent_app_number] => 641820 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641820
Memory interface with address shift for different memory types May 1, 1996 Issued
Array ( [id] => 3898044 [patent_doc_number] => 05765191 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-09 [patent_title] => 'Method for implementing a four-way least recently used (LRU) mechanism in high-performance' [patent_app_type] => 1 [patent_app_number] => 8/641060 [patent_app_country] => US [patent_app_date] => 1996-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3711 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/765/05765191.pdf [firstpage_image] =>[orig_patent_app_number] => 641060 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/641060
Method for implementing a four-way least recently used (LRU) mechanism in high-performance Apr 28, 1996 Issued
Array ( [id] => 3638396 [patent_doc_number] => 05608891 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-03-04 [patent_title] => 'Recording system having a redundant array of storage devices and having read and write circuits with memory buffers' [patent_app_type] => 1 [patent_app_number] => 8/634140 [patent_app_country] => US [patent_app_date] => 1996-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 33 [patent_no_of_words] => 12800 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/608/05608891.pdf [firstpage_image] =>[orig_patent_app_number] => 634140 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/634140
Recording system having a redundant array of storage devices and having read and write circuits with memory buffers Apr 18, 1996 Issued
Array ( [id] => 3701811 [patent_doc_number] => 05604883 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-18 [patent_title] => 'Computer memory open page bias method and system' [patent_app_type] => 1 [patent_app_number] => 8/629789 [patent_app_country] => US [patent_app_date] => 1996-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3730 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/604/05604883.pdf [firstpage_image] =>[orig_patent_app_number] => 629789 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/629789
Computer memory open page bias method and system Apr 8, 1996 Issued
Array ( [id] => 3767294 [patent_doc_number] => 05721867 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Method and apparatus for executing single beat write store instructions during a cache store linefill operation' [patent_app_type] => 1 [patent_app_number] => 8/630870 [patent_app_country] => US [patent_app_date] => 1996-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3021 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721867.pdf [firstpage_image] =>[orig_patent_app_number] => 630870 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/630870
Method and apparatus for executing single beat write store instructions during a cache store linefill operation Mar 31, 1996 Issued
08/623266 CACHE MULTI-BLOCK TOUCH MECHANISM FOR OBJECT ORIENTED COMPUTER SYSTEM Mar 27, 1996 Abandoned
Array ( [id] => 3843369 [patent_doc_number] => 05784697 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Process assignment by nodal affinity in a myultiprocessor system having non-uniform memory access storage architecture' [patent_app_type] => 1 [patent_app_number] => 8/622230 [patent_app_country] => US [patent_app_date] => 1996-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4054 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784697.pdf [firstpage_image] =>[orig_patent_app_number] => 622230 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622230
Process assignment by nodal affinity in a myultiprocessor system having non-uniform memory access storage architecture Mar 26, 1996 Issued
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