Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3805961 [patent_doc_number] => 05737751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system' [patent_app_type] => 1 [patent_app_number] => 8/622254 [patent_app_country] => US [patent_app_date] => 1996-03-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4216 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737751.pdf [firstpage_image] =>[orig_patent_app_number] => 622254 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/622254
Cache memory management system having reduced reloads to a second level cache for enhanced memory performance in a data processing system Mar 25, 1996 Issued
Array ( [id] => 3806129 [patent_doc_number] => 05737763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Incremental disk backup' [patent_app_type] => 1 [patent_app_number] => 8/620470 [patent_app_country] => US [patent_app_date] => 1996-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1764 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737763.pdf [firstpage_image] =>[orig_patent_app_number] => 620470 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/620470
Incremental disk backup Mar 21, 1996 Issued
Array ( [id] => 3805998 [patent_doc_number] => 05737754 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-04-07 [patent_title] => 'Cache memory which selects one of several blocks to update by digitally combining control bits in all the blocks' [patent_app_type] => 1 [patent_app_number] => 8/619050 [patent_app_country] => US [patent_app_date] => 1996-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5560 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/737/05737754.pdf [firstpage_image] =>[orig_patent_app_number] => 619050 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/619050
Cache memory which selects one of several blocks to update by digitally combining control bits in all the blocks Mar 19, 1996 Issued
Array ( [id] => 3908099 [patent_doc_number] => 05778420 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'External storage device and external storage control device with means for optimizing buffer full/empty ratio' [patent_app_type] => 1 [patent_app_number] => 8/608336 [patent_app_country] => US [patent_app_date] => 1996-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 14642 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778420.pdf [firstpage_image] =>[orig_patent_app_number] => 608336 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/608336
External storage device and external storage control device with means for optimizing buffer full/empty ratio Feb 27, 1996 Issued
Array ( [id] => 3913404 [patent_doc_number] => 05835951 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Branch processing unit with target cache read prioritization protocol for handling multiple hits' [patent_app_type] => 1 [patent_app_number] => 8/606770 [patent_app_country] => US [patent_app_date] => 1996-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 30 [patent_no_of_words] => 23844 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835951.pdf [firstpage_image] =>[orig_patent_app_number] => 606770 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/606770
Branch processing unit with target cache read prioritization protocol for handling multiple hits Feb 26, 1996 Issued
08/607188 INFORMATION COMMUNICATION SYSTEM WHICH TRANSMITS MAIN DATA AND DATA FOR RESTORING THE MAIN DATA Feb 25, 1996 Abandoned
Array ( [id] => 3716547 [patent_doc_number] => 05675768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Store software instrumentation package instruction' [patent_app_type] => 1 [patent_app_number] => 8/595372 [patent_app_country] => US [patent_app_date] => 1996-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3241 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675768.pdf [firstpage_image] =>[orig_patent_app_number] => 595372 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/595372
Store software instrumentation package instruction Jan 31, 1996 Issued
Array ( [id] => 3908261 [patent_doc_number] => 05778431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-07 [patent_title] => 'System and apparatus for partially flushing cache memory' [patent_app_type] => 1 [patent_app_number] => 8/575684 [patent_app_country] => US [patent_app_date] => 1995-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4893 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/778/05778431.pdf [firstpage_image] =>[orig_patent_app_number] => 575684 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/575684
System and apparatus for partially flushing cache memory Dec 18, 1995 Issued
Array ( [id] => 3660373 [patent_doc_number] => 05640533 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-17 [patent_title] => 'Translation lookaside buffer (TLB) arrangement wherein the TLB contents are retained from task when it is swapped out and reloaded when the task is rescheduled' [patent_app_type] => 1 [patent_app_number] => 8/571455 [patent_app_country] => US [patent_app_date] => 1995-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3524 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/640/05640533.pdf [firstpage_image] =>[orig_patent_app_number] => 571455 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/571455
Translation lookaside buffer (TLB) arrangement wherein the TLB contents are retained from task when it is swapped out and reloaded when the task is rescheduled Dec 12, 1995 Issued
Array ( [id] => 4423733 [patent_doc_number] => 06240496 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-29 [patent_title] => 'Architecture and configuring method for a computer expansion board' [patent_app_type] => 1 [patent_app_number] => 8/570256 [patent_app_country] => US [patent_app_date] => 1995-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1600 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/240/06240496.pdf [firstpage_image] =>[orig_patent_app_number] => 570256 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/570256
Architecture and configuring method for a computer expansion board Dec 10, 1995 Issued
Array ( [id] => 3913525 [patent_doc_number] => 05835959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-11-10 [patent_title] => 'Memory management system and method using dual indexing structures' [patent_app_type] => 1 [patent_app_number] => 8/565862 [patent_app_country] => US [patent_app_date] => 1995-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 26 [patent_no_of_words] => 12018 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/835/05835959.pdf [firstpage_image] =>[orig_patent_app_number] => 565862 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/565862
Memory management system and method using dual indexing structures Nov 30, 1995 Issued
Array ( [id] => 3871144 [patent_doc_number] => 05706472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Method for manipulating disk partitions' [patent_app_type] => 1 [patent_app_number] => 8/554828 [patent_app_country] => US [patent_app_date] => 1995-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 14403 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706472.pdf [firstpage_image] =>[orig_patent_app_number] => 554828 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/554828
Method for manipulating disk partitions Nov 6, 1995 Issued
Array ( [id] => 3767374 [patent_doc_number] => 05721873 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-02-24 [patent_title] => 'Data reproducing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/540222 [patent_app_country] => US [patent_app_date] => 1995-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5602 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/721/05721873.pdf [firstpage_image] =>[orig_patent_app_number] => 540222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/540222
Data reproducing apparatus Oct 5, 1995 Issued
Array ( [id] => 3843429 [patent_doc_number] => 05784701 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Method and system for dynamically changing the size of a hardware system area' [patent_app_type] => 1 [patent_app_number] => 8/530784 [patent_app_country] => US [patent_app_date] => 1995-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3207 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784701.pdf [firstpage_image] =>[orig_patent_app_number] => 530784 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/530784
Method and system for dynamically changing the size of a hardware system area Sep 18, 1995 Issued
Array ( [id] => 3824929 [patent_doc_number] => 05710906 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-20 [patent_title] => 'Predictive snooping of cache memory for master-initiated accesses' [patent_app_type] => 1 [patent_app_number] => 8/499610 [patent_app_country] => US [patent_app_date] => 1995-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 18452 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/710/05710906.pdf [firstpage_image] =>[orig_patent_app_number] => 499610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/499610
Predictive snooping of cache memory for master-initiated accesses Jul 6, 1995 Issued
Array ( [id] => 3967377 [patent_doc_number] => 05983328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Data processing device with time-multiplexed memory bus' [patent_app_type] => 1 [patent_app_number] => 8/479543 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 20611 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983328.pdf [firstpage_image] =>[orig_patent_app_number] => 479543 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479543
Data processing device with time-multiplexed memory bus Jun 6, 1995 Issued
Array ( [id] => 3716575 [patent_doc_number] => 05675770 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-10-07 [patent_title] => 'Memory controller having means for comparing a designated address with addresses setting an area in a memory' [patent_app_type] => 1 [patent_app_number] => 8/479465 [patent_app_country] => US [patent_app_date] => 1995-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 18 [patent_no_of_words] => 6353 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/675/05675770.pdf [firstpage_image] =>[orig_patent_app_number] => 479465 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/479465
Memory controller having means for comparing a designated address with addresses setting an area in a memory Jun 6, 1995 Issued
Array ( [id] => 3782697 [patent_doc_number] => 05850534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-12-15 [patent_title] => 'Method and apparatus for reducing cache snooping overhead in a multilevel cache system' [patent_app_type] => 1 [patent_app_number] => 8/464350 [patent_app_country] => US [patent_app_date] => 1995-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4539 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/850/05850534.pdf [firstpage_image] =>[orig_patent_app_number] => 464350 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/464350
Method and apparatus for reducing cache snooping overhead in a multilevel cache system Jun 4, 1995 Issued
08/452274 LINKED CACHE MEMORY FOR STORING UNITS OF INFORMATION May 25, 1995 Abandoned
Array ( [id] => 3844204 [patent_doc_number] => 05713004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-27 [patent_title] => 'Cache control for use in a multiprocessor to prevent data from ping-ponging between caches' [patent_app_type] => 1 [patent_app_number] => 8/443604 [patent_app_country] => US [patent_app_date] => 1995-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3909 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/713/05713004.pdf [firstpage_image] =>[orig_patent_app_number] => 443604 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/443604
Cache control for use in a multiprocessor to prevent data from ping-ponging between caches May 17, 1995 Issued
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