| Application number | Title of the application | Filing Date | Status |
|---|
Array
(
[id] => 3625704
[patent_doc_number] => 05566322
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Method and apparatus for performing read accesses from a counter which avoid large rollover error when multiple read access cycles are used'
[patent_app_type] => 1
[patent_app_number] => 8/154774
[patent_app_country] => US
[patent_app_date] => 1993-11-19
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[firstpage_image] =>[orig_patent_app_number] => 154774
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/154774 | Method and apparatus for performing read accesses from a counter which avoid large rollover error when multiple read access cycles are used | Nov 18, 1993 | Issued |
Array
(
[id] => 3612436
[patent_doc_number] => 05559993
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-24
[patent_title] => 'Hardware circuit for securing a computer against undesired write and/or read operations'
[patent_app_type] => 1
[patent_app_number] => 8/153164
[patent_app_country] => US
[patent_app_date] => 1993-11-17
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/559/05559993.pdf
[firstpage_image] =>[orig_patent_app_number] => 153164
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/153164 | Hardware circuit for securing a computer against undesired write and/or read operations | Nov 16, 1993 | Issued |
Array
(
[id] => 3569757
[patent_doc_number] => 05544345
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-08-06
[patent_title] => 'Coherence controls for store-multiple shared data coordinated by cache directory entries in a shared electronic storage'
[patent_app_type] => 1
[patent_app_number] => 8/148707
[patent_app_country] => US
[patent_app_date] => 1993-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 22
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[patent_no_of_words] => 22937
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[pdf_file] => patents/05/544/05544345.pdf
[firstpage_image] =>[orig_patent_app_number] => 148707
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/148707 | Coherence controls for store-multiple shared data coordinated by cache directory entries in a shared electronic storage | Nov 7, 1993 | Issued |
| 08/147817 | DISK ARRAY APPARATUS | Nov 3, 1993 | Abandoned |
Array
(
[id] => 3943615
[patent_doc_number] => 05878245
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1999-03-02
[patent_title] => 'High performance load/store functional unit and data cache'
[patent_app_type] => 1
[patent_app_number] => 8/146376
[patent_app_country] => US
[patent_app_date] => 1993-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 23
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[pdf_file] => patents/05/878/05878245.pdf
[firstpage_image] =>[orig_patent_app_number] => 146376
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/146376 | High performance load/store functional unit and data cache | Oct 28, 1993 | Issued |
| 08/139746 | ASYNCHRONOUS ACCESS SYSTEM FOR SHARED MEMORY | Oct 21, 1993 | Abandoned |
Array
(
[id] => 3661627
[patent_doc_number] => 05606687
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-25
[patent_title] => 'Method and apparatus for optimizing supervisor mode store operations in a data cache'
[patent_app_type] => 1
[patent_app_number] => 8/132795
[patent_app_country] => US
[patent_app_date] => 1993-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/606/05606687.pdf
[firstpage_image] =>[orig_patent_app_number] => 132795
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/132795 | Method and apparatus for optimizing supervisor mode store operations in a data cache | Oct 6, 1993 | Issued |
Array
(
[id] => 3521749
[patent_doc_number] => 05588135
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-24
[patent_title] => 'Data processing device in a virtual memory having a paging function'
[patent_app_type] => 1
[patent_app_number] => 8/133220
[patent_app_country] => US
[patent_app_date] => 1993-10-07
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/588/05588135.pdf
[firstpage_image] =>[orig_patent_app_number] => 133220
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/133220 | Data processing device in a virtual memory having a paging function | Oct 6, 1993 | Issued |
| 08/131829 | SCALED MEMORY ALLOCATION SYSTEM | Oct 4, 1993 | Abandoned |
| 08/132170 | A RECORDING SYSTEM HAVING A REDUNDANT ARRAY OF STORAGE DEVICES AND HAVING READ AND WRITE CIRCUITS WITH MEMORY BUFFERS | Oct 4, 1993 | Abandoned |
Array
(
[id] => 4381170
[patent_doc_number] => 06256704
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2001-07-03
[patent_title] => 'Task management for data accesses to multiple logical partitions on physical disk drives in computer systems'
[patent_app_type] => 1
[patent_app_number] => 8/122828
[patent_app_country] => US
[patent_app_date] => 1993-09-16
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[pdf_file] => patents/06/256/06256704.pdf
[firstpage_image] =>[orig_patent_app_number] => 122828
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/122828 | Task management for data accesses to multiple logical partitions on physical disk drives in computer systems | Sep 15, 1993 | Issued |
Array
(
[id] => 3621339
[patent_doc_number] => 05590308
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-12-31
[patent_title] => 'Method and apparatus for reducing false invalidations in distributed systems'
[patent_app_type] => 1
[patent_app_number] => 8/115501
[patent_app_country] => US
[patent_app_date] => 1993-09-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[pdf_file] => patents/05/590/05590308.pdf
[firstpage_image] =>[orig_patent_app_number] => 115501
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/115501 | Method and apparatus for reducing false invalidations in distributed systems | Aug 31, 1993 | Issued |
Array
(
[id] => 3600142
[patent_doc_number] => 05553263
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-09-03
[patent_title] => 'Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory'
[patent_app_type] => 1
[patent_app_number] => 8/092835
[patent_app_country] => US
[patent_app_date] => 1993-07-16
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[pdf_file] => patents/05/553/05553263.pdf
[firstpage_image] =>[orig_patent_app_number] => 092835
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/092835 | Cache memory system with fault tolerance having concurrently operational cache controllers processing disjoint groups of memory | Jul 15, 1993 | Issued |
Array
(
[id] => 4200052
[patent_doc_number] => 06021477
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 2000-02-01
[patent_title] => 'Multiple mode memory module'
[patent_app_type] => 1
[patent_app_number] => 8/092628
[patent_app_country] => US
[patent_app_date] => 1993-07-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
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[pdf_file] => patents/06/021/06021477.pdf
[firstpage_image] =>[orig_patent_app_number] => 092628
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/092628 | Multiple mode memory module | Jul 14, 1993 | Issued |
| 08/088205 | A CPU WRITE-BACK CACHE COHERENCY MECHANISM THAT TRANSFERS DATA FROM A CACHE MEMORY TO A MAIN MEMORY BEFORE ACCESS OF THE MAIN MEMORY BY AN ALTERNATE BUS MASTER | Jul 5, 1993 | Pending |
Array
(
[id] => 3625680
[patent_doc_number] => 05566320
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-10-15
[patent_title] => 'Memory storage access control circuit for coupled mask-programmed microcontrollers'
[patent_app_type] => 1
[patent_app_number] => 8/086925
[patent_app_country] => US
[patent_app_date] => 1993-07-02
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/566/05566320.pdf
[firstpage_image] =>[orig_patent_app_number] => 086925
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/086925 | Memory storage access control circuit for coupled mask-programmed microcontrollers | Jul 1, 1993 | Issued |
Array
(
[id] => 3674609
[patent_doc_number] => 05657476
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-08-12
[patent_title] => 'Signal processor with delay line management logic'
[patent_app_type] => 1
[patent_app_number] => 8/078726
[patent_app_country] => US
[patent_app_date] => 1993-06-17
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[firstpage_image] =>[orig_patent_app_number] => 078726
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/078726 | Signal processor with delay line management logic | Jun 16, 1993 | Issued |
Array
(
[id] => 3505750
[patent_doc_number] => 05537578
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1996-07-16
[patent_title] => 'Transparent driving partition for processing logical volumes to be recorded onto optical media'
[patent_app_type] => 1
[patent_app_number] => 8/049470
[patent_app_country] => US
[patent_app_date] => 1993-04-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/537/05537578.pdf
[firstpage_image] =>[orig_patent_app_number] => 049470
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/049470 | Transparent driving partition for processing logical volumes to be recorded onto optical media | Apr 19, 1993 | Issued |
Array
(
[id] => 3701821
[patent_doc_number] => 05604884
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1997-02-18
[patent_title] => 'Burst SRAMS for use with a high speed clock'
[patent_app_type] => 1
[patent_app_number] => 8/034288
[patent_app_country] => US
[patent_app_date] => 1993-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => patents/05/604/05604884.pdf
[firstpage_image] =>[orig_patent_app_number] => 034288
[rel_patent_id] =>[rel_patent_doc_number] =>) 08/034288 | Burst SRAMS for use with a high speed clock | Mar 21, 1993 | Issued |
| 08/023033 | SYSTEM FOR INTERLEAVING MEMORY MODULES AND BANKS | Feb 23, 1993 | Abandoned |