Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3843457 [patent_doc_number] => 05784703 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Storage system having logical subsystems configured in accordance with equally divided storage capacities, specified allotment rates, designated boundary positions or designated physical size' [patent_app_type] => 1 [patent_app_number] => 8/016394 [patent_app_country] => US [patent_app_date] => 1993-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4487 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784703.pdf [firstpage_image] =>[orig_patent_app_number] => 016394 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/016394
Storage system having logical subsystems configured in accordance with equally divided storage capacities, specified allotment rates, designated boundary positions or designated physical size Feb 10, 1993 Issued
Array ( [id] => 1438691 [patent_doc_number] => 06356989 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Translation lookaside buffer (TLB) arrangement wherein the TLB contents retained for a task as swapped out and reloaded when a task is rescheduled' [patent_app_type] => B1 [patent_app_number] => 07/993783 [patent_app_country] => US [patent_app_date] => 1992-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3527 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356989.pdf [firstpage_image] =>[orig_patent_app_number] => 07993783 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/993783
Translation lookaside buffer (TLB) arrangement wherein the TLB contents retained for a task as swapped out and reloaded when a task is rescheduled Dec 20, 1992 Issued
Array ( [id] => 3742737 [patent_doc_number] => 05704057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Real-time data sorter' [patent_app_type] => 1 [patent_app_number] => 7/955388 [patent_app_country] => US [patent_app_date] => 1992-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2165 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/704/05704057.pdf [firstpage_image] =>[orig_patent_app_number] => 955388 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/955388
Real-time data sorter Sep 30, 1992 Issued
Array ( [id] => 3674514 [patent_doc_number] => 05657471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-08-12 [patent_title] => 'Dual addressing arrangement for a communications interface architecture' [patent_app_type] => 1 [patent_app_number] => 7/870491 [patent_app_country] => US [patent_app_date] => 1992-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5522 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 241 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/657/05657471.pdf [firstpage_image] =>[orig_patent_app_number] => 870491 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/870491
Dual addressing arrangement for a communications interface architecture Apr 15, 1992 Issued
07/563221 COMPUTER MEMORY OPEN PAGE BIAS MEHTOD AND SYSTEM Aug 5, 1990 Abandoned
Menu