Search

Sarira Camilla Pourbohloul

Examiner (ID: 426, Phone: (571)270-7744 , Office: P/1765 )

Most Active Art Unit
1765
Art Unit(s)
1765, 1796
Total Applications
236
Issued Applications
141
Pending Applications
1
Abandoned Applications
95

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7214160 [patent_doc_number] => 20050044328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Methods and apparatus for maintaining coherency in a multi-processor system' [patent_app_type] => utility [patent_app_number] => 10/645742 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3838 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044328.pdf [firstpage_image] =>[orig_patent_app_number] => 10645742 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645742
Methods and apparatus for maintaining coherency in a multi-processor system Aug 20, 2003 Issued
Array ( [id] => 615719 [patent_doc_number] => 07149851 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-12 [patent_title] => 'Method and system for conservatively managing store capacity available to a processor issuing stores' [patent_app_type] => utility [patent_app_number] => 10/646461 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4931 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149851.pdf [firstpage_image] =>[orig_patent_app_number] => 10646461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/646461
Method and system for conservatively managing store capacity available to a processor issuing stores Aug 20, 2003 Issued
Array ( [id] => 7214056 [patent_doc_number] => 20050044313 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Grouping of storage media based on parameters associated with the storage media' [patent_app_type] => utility [patent_app_number] => 10/645129 [patent_app_country] => US [patent_app_date] => 2003-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8317 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20050044313.pdf [firstpage_image] =>[orig_patent_app_number] => 10645129 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/645129
Grouping of storage media based on parameters associated with the storage media Aug 20, 2003 Issued
Array ( [id] => 705139 [patent_doc_number] => 07069411 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-06-27 [patent_title] => 'Mapper circuit with backup capability' [patent_app_type] => utility [patent_app_number] => 10/633899 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8918 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/069/07069411.pdf [firstpage_image] =>[orig_patent_app_number] => 10633899 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633899
Mapper circuit with backup capability Aug 3, 2003 Issued
Array ( [id] => 731061 [patent_doc_number] => 07047361 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-16 [patent_title] => 'Data storage device using SDRAM' [patent_app_type] => utility [patent_app_number] => 10/632924 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1391 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/047/07047361.pdf [firstpage_image] =>[orig_patent_app_number] => 10632924 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/632924
Data storage device using SDRAM Aug 3, 2003 Issued
Array ( [id] => 7036218 [patent_doc_number] => 20050033933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Systems and methods for modifying disk drive firmware in a raid storage system' [patent_app_type] => utility [patent_app_number] => 10/633801 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3632 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20050033933.pdf [firstpage_image] =>[orig_patent_app_number] => 10633801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633801
Systems and methods for modifying disk drive firmware in a raid storage system Aug 3, 2003 Abandoned
Array ( [id] => 685451 [patent_doc_number] => 07082513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-25 [patent_title] => 'Integrated memory and method for checking the functioning of an integrated memory' [patent_app_type] => utility [patent_app_number] => 10/633996 [patent_app_country] => US [patent_app_date] => 2003-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4813 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/082/07082513.pdf [firstpage_image] =>[orig_patent_app_number] => 10633996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/633996
Integrated memory and method for checking the functioning of an integrated memory Aug 3, 2003 Issued
Array ( [id] => 7174181 [patent_doc_number] => 20040078536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Authentication mechanism integrated with random access memory and method of use' [patent_app_type] => new [patent_app_number] => 10/630507 [patent_app_country] => US [patent_app_date] => 2003-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4305 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0078/20040078536.pdf [firstpage_image] =>[orig_patent_app_number] => 10630507 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630507
Authentication mechanism integrated with random access memory and method of use Jul 27, 2003 Abandoned
Array ( [id] => 7328567 [patent_doc_number] => 20040139245 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-15 [patent_title] => 'Predictive snooping of cache memory for master-initiated accesses' [patent_app_type] => new [patent_app_number] => 10/619798 [patent_app_country] => US [patent_app_date] => 2003-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 18613 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0139/20040139245.pdf [firstpage_image] =>[orig_patent_app_number] => 10619798 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/619798
Predictive snooping of cache memory for master-initiated accesses Jul 14, 2003 Abandoned
Array ( [id] => 7367448 [patent_doc_number] => 20040015650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-22 [patent_title] => 'Method and apparatus for utilizing write buffers in memory control/interface memory control translators' [patent_app_type] => new [patent_app_number] => 10/618885 [patent_app_country] => US [patent_app_date] => 2003-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4953 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0015/20040015650.pdf [firstpage_image] =>[orig_patent_app_number] => 10618885 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/618885
Memory control translators Jul 13, 2003 Issued
Array ( [id] => 5695806 [patent_doc_number] => 20060155953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-07-13 [patent_title] => 'Method and apparatus for accessing multiple vector elements in parallel' [patent_app_type] => utility [patent_app_number] => 10/522085 [patent_app_country] => US [patent_app_date] => 2003-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2543 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20060155953.pdf [firstpage_image] =>[orig_patent_app_number] => 10522085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/522085
Method and apparatus for accessing multiple vector elements in parallel Jul 9, 2003 Abandoned
Array ( [id] => 950047 [patent_doc_number] => 06963950 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Multi-processor type storage control apparatus for performing access control through selector' [patent_app_type] => utility [patent_app_number] => 10/613154 [patent_app_country] => US [patent_app_date] => 2003-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13110 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963950.pdf [firstpage_image] =>[orig_patent_app_number] => 10613154 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/613154
Multi-processor type storage control apparatus for performing access control through selector Jul 6, 2003 Issued
Array ( [id] => 609484 [patent_doc_number] => 07155577 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-26 [patent_title] => 'Optimistic reads in a multi-node environment' [patent_app_type] => utility [patent_app_number] => 10/610193 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12219 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/155/07155577.pdf [firstpage_image] =>[orig_patent_app_number] => 10610193 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/610193
Optimistic reads in a multi-node environment Jun 29, 2003 Issued
Array ( [id] => 485560 [patent_doc_number] => 07225293 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Method, system, and program for executing input/output requests' [patent_app_type] => utility [patent_app_number] => 10/463012 [patent_app_country] => US [patent_app_date] => 2003-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4254 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225293.pdf [firstpage_image] =>[orig_patent_app_number] => 10463012 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/463012
Method, system, and program for executing input/output requests Jun 15, 2003 Issued
Array ( [id] => 1070958 [patent_doc_number] => 06845430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-18 [patent_title] => 'System for maintaining a buffer pool' [patent_app_type] => utility [patent_app_number] => 10/452461 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6215 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/845/06845430.pdf [firstpage_image] =>[orig_patent_app_number] => 10452461 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/452461
System for maintaining a buffer pool Jun 1, 2003 Issued
Array ( [id] => 645500 [patent_doc_number] => 07124241 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Apparatus and methodology for a write hub that supports high speed and low speed data rates' [patent_app_type] => utility [patent_app_number] => 10/431875 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 15280 [patent_no_of_claims] => 85 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/124/07124241.pdf [firstpage_image] =>[orig_patent_app_number] => 10431875 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431875
Apparatus and methodology for a write hub that supports high speed and low speed data rates May 6, 2003 Issued
Array ( [id] => 955114 [patent_doc_number] => 06959362 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-25 [patent_title] => 'Caching based on access rights in connection with a content management server system or the like' [patent_app_type] => utility [patent_app_number] => 10/431408 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5865 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/959/06959362.pdf [firstpage_image] =>[orig_patent_app_number] => 10431408 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431408
Caching based on access rights in connection with a content management server system or the like May 6, 2003 Issued
Array ( [id] => 937552 [patent_doc_number] => 06976142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Method and system to provide simultaneous access by multiple pipelines to a table' [patent_app_type] => utility [patent_app_number] => 10/431974 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7396 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/976/06976142.pdf [firstpage_image] =>[orig_patent_app_number] => 10431974 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431974
Method and system to provide simultaneous access by multiple pipelines to a table May 6, 2003 Issued
Array ( [id] => 713197 [patent_doc_number] => 07062606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events' [patent_app_type] => utility [patent_app_number] => 10/431996 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 5342 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/062/07062606.pdf [firstpage_image] =>[orig_patent_app_number] => 10431996 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431996
Multi-threaded embedded processor using deterministic instruction memory to guarantee execution of pre-selected threads during blocking events May 6, 2003 Issued
Array ( [id] => 958124 [patent_doc_number] => 06957312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-10-18 [patent_title] => 'NVRAM control protocol' [patent_app_type] => utility [patent_app_number] => 10/431995 [patent_app_country] => US [patent_app_date] => 2003-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5251 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957312.pdf [firstpage_image] =>[orig_patent_app_number] => 10431995 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/431995
NVRAM control protocol May 6, 2003 Issued
Menu