
Saul Bergmann
Examiner (ID: 17512)
| Most Active Art Unit | 2107 |
| Art Unit(s) | 2107, 2899 |
| Total Applications | 698 |
| Issued Applications | 664 |
| Pending Applications | 0 |
| Abandoned Applications | 34 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 17686725
[patent_doc_number] => 20220194017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-23
[patent_title] => METHODS AND APPARATUS FOR INDUCTION WELDING
[patent_app_type] => utility
[patent_app_number] => 17/515383
[patent_app_country] => US
[patent_app_date] => 2021-10-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10915
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17515383
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/515383 | U-shaped induction welding coil and method of use thereof | Oct 28, 2021 | Issued |
Array
(
[id] => 19487249
[patent_doc_number] => 12106973
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-10-01
[patent_title] => Two-step decapsulation technique for semiconductor package having silver bond wires
[patent_app_type] => utility
[patent_app_number] => 17/513037
[patent_app_country] => US
[patent_app_date] => 2021-10-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 6
[patent_no_of_words] => 3095
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17513037
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/513037 | Two-step decapsulation technique for semiconductor package having silver bond wires | Oct 27, 2021 | Issued |
Array
(
[id] => 18983655
[patent_doc_number] => 11908844
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-02-20
[patent_title] => Multilayer power, converter with devices having reduced lateral current
[patent_app_type] => utility
[patent_app_number] => 17/452275
[patent_app_country] => US
[patent_app_date] => 2021-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 28
[patent_no_of_words] => 6661
[patent_no_of_claims] => 29
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 70
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17452275
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/452275 | Multilayer power, converter with devices having reduced lateral current | Oct 25, 2021 | Issued |
Array
(
[id] => 18623869
[patent_doc_number] => 11756925
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-09-12
[patent_title] => Methods and apparatus for vacuum processing a substrate
[patent_app_type] => utility
[patent_app_number] => 17/508489
[patent_app_country] => US
[patent_app_date] => 2021-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3678
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17508489
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/508489 | Methods and apparatus for vacuum processing a substrate | Oct 21, 2021 | Issued |
Array
(
[id] => 17371584
[patent_doc_number] => 20220026636
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-01-27
[patent_title] => MULTILEVEL SEMICONDUCTOR DEVICE AND STRUCTURE WITH ELECTROMAGNETIC MODULATORS
[patent_app_type] => utility
[patent_app_number] => 17/492627
[patent_app_country] => US
[patent_app_date] => 2021-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13056
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492627
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/492627 | Multilevel semiconductor device and structure with electromagnetic modulators | Oct 2, 2021 | Issued |
Array
(
[id] => 17787777
[patent_doc_number] => 11410912
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-08-09
[patent_title] => 3D semiconductor device with vias and isolation layers
[patent_app_type] => utility
[patent_app_number] => 17/492577
[patent_app_country] => US
[patent_app_date] => 2021-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 63
[patent_figures_cnt] => 64
[patent_no_of_words] => 17228
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 148
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17492577
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/492577 | 3D semiconductor device with vias and isolation layers | Oct 1, 2021 | Issued |
Array
(
[id] => 19428184
[patent_doc_number] => 12087617
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-09-10
[patent_title] => Formation method for air spacer layer and semiconductor structure
[patent_app_type] => utility
[patent_app_number] => 17/487854
[patent_app_country] => US
[patent_app_date] => 2021-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 5103
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487854
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/487854 | Formation method for air spacer layer and semiconductor structure | Sep 27, 2021 | Issued |
Array
(
[id] => 18284355
[patent_doc_number] => 20230099827
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => TECHNOLOGIES FOR HIGH THROUGHPUT ADDITIVE MANUFACTURING FOR INTEGRATED CIRCUIT COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 17/484281
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 16568
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17484281
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/484281 | High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries | Sep 23, 2021 | Issued |
Array
(
[id] => 18285906
[patent_doc_number] => 20230101378
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-30
[patent_title] => SEMICONDUCTOR DIES AND DEVICES WITH COILS FOR INDUCTIVE COUPLING
[patent_app_type] => utility
[patent_app_number] => 17/448738
[patent_app_country] => US
[patent_app_date] => 2021-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7399
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 51
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17448738
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/448738 | Semiconductor dies and devices with frontside and backside coils for inductive coupling | Sep 23, 2021 | Issued |
Array
(
[id] => 17481200
[patent_doc_number] => 20220088704
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-24
[patent_title] => MULTI-SOURCE LASER HEAD FOR LASER ENGRAVING
[patent_app_type] => utility
[patent_app_number] => 17/476233
[patent_app_country] => US
[patent_app_date] => 2021-09-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6285
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476233
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/476233 | MULTI-SOURCE LASER HEAD FOR LASER ENGRAVING | Sep 14, 2021 | Abandoned |
Array
(
[id] => 17870792
[patent_doc_number] => 20220293529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-09-15
[patent_title] => SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/471059
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8135
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17471059
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/471059 | Semiconductor device with multilayer insulating layer in recess and method of manufacturing the same | Sep 8, 2021 | Issued |
Array
(
[id] => 19767390
[patent_doc_number] => 12225706
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-11
[patent_title] => Semiconductor device with passivated contact plugs, semiconductor structure and manufacturing method thereof
[patent_app_type] => utility
[patent_app_number] => 17/447218
[patent_app_country] => US
[patent_app_date] => 2021-09-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 13
[patent_no_of_words] => 6839
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 124
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447218
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/447218 | Semiconductor device with passivated contact plugs, semiconductor structure and manufacturing method thereof | Sep 8, 2021 | Issued |
Array
(
[id] => 18723321
[patent_doc_number] => 11800699
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-10-24
[patent_title] => Semiconductor structure with chamfered capacitor connection line adjacent bit line and method for manufacturing semiconductor structure thereof
[patent_app_type] => utility
[patent_app_number] => 17/447137
[patent_app_country] => US
[patent_app_date] => 2021-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 16
[patent_no_of_words] => 6014
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 217
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17447137
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/447137 | Semiconductor structure with chamfered capacitor connection line adjacent bit line and method for manufacturing semiconductor structure thereof | Sep 7, 2021 | Issued |
Array
(
[id] => 18840270
[patent_doc_number] => 11848352
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-12-19
[patent_title] => Metal-insulator-metal capacitors and methods of forming the same
[patent_app_type] => utility
[patent_app_number] => 17/467686
[patent_app_country] => US
[patent_app_date] => 2021-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 38
[patent_figures_cnt] => 38
[patent_no_of_words] => 13347
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 99
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467686
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/467686 | Metal-insulator-metal capacitors and methods of forming the same | Sep 6, 2021 | Issued |
Array
(
[id] => 19781494
[patent_doc_number] => 12230532
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-02-18
[patent_title] => Semiconductor device, method of manufacture by monitoring relative humidity, and system of manufacture thereof
[patent_app_type] => utility
[patent_app_number] => 17/459509
[patent_app_country] => US
[patent_app_date] => 2021-08-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 68
[patent_figures_cnt] => 96
[patent_no_of_words] => 17433
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459509
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/459509 | Semiconductor device, method of manufacture by monitoring relative humidity, and system of manufacture thereof | Aug 26, 2021 | Issued |
Array
(
[id] => 18227342
[patent_doc_number] => 20230066336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-03-02
[patent_title] => GALLIUM NITRIDE (GAN) EPITAXY ON PATTERNED SUBSTRATE FOR INTEGRATED CIRCUIT TECHNOLOGY
[patent_app_type] => utility
[patent_app_number] => 17/458112
[patent_app_country] => US
[patent_app_date] => 2021-08-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15431
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17458112
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/458112 | GALLIUM NITRIDE (GAN) EPITAXY ON PATTERNED SUBSTRATE FOR INTEGRATED CIRCUIT TECHNOLOGY | Aug 25, 2021 | Pending |
Array
(
[id] => 18548267
[patent_doc_number] => 11721627
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-08-08
[patent_title] => Graphene layer for reduced contact resistance
[patent_app_type] => utility
[patent_app_number] => 17/403267
[patent_app_country] => US
[patent_app_date] => 2021-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 4568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 54
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17403267
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/403267 | Graphene layer for reduced contact resistance | Aug 15, 2021 | Issued |
Array
(
[id] => 17532858
[patent_doc_number] => 20220111467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-14
[patent_title] => METHODS TO FABRICATE CHAMBER COMPONENT USING LASER DRILLING
[patent_app_type] => utility
[patent_app_number] => 17/392248
[patent_app_country] => US
[patent_app_date] => 2021-08-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6232
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392248
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/392248 | Methods to fabricate chamber component holes using laser drilling | Aug 1, 2021 | Issued |
Array
(
[id] => 17645254
[patent_doc_number] => 20220172993
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-06-02
[patent_title] => METHOD OF DICING WAFER
[patent_app_type] => utility
[patent_app_number] => 17/388779
[patent_app_country] => US
[patent_app_date] => 2021-07-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6996
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 131
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17388779
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/388779 | Method of dicing wafer forming modified layer in chucked wafer | Jul 28, 2021 | Issued |
Array
(
[id] => 19241368
[patent_doc_number] => 12011784
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-06-18
[patent_title] => Wafer, wafer manufacturing method, device chip manufacturing method, and resistivity markings
[patent_app_type] => utility
[patent_app_number] => 17/382921
[patent_app_country] => US
[patent_app_date] => 2021-07-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 19
[patent_no_of_words] => 9763
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17382921
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/382921 | Wafer, wafer manufacturing method, device chip manufacturing method, and resistivity markings | Jul 21, 2021 | Issued |