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Saumit Shah

Examiner (ID: 16826, Phone: (571)272-6959 , Office: P/2414 )

Most Active Art Unit
2414
Art Unit(s)
2414
Total Applications
605
Issued Applications
465
Pending Applications
88
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
08/454795 LOW OVERHEAD INPUT AND OUTPUT BOUNDARY SCAN CELLS May 30, 1995 Abandoned
08/434882 INTEGRAL BIT ERROR RATE TEST SYSTEM FOR SERIAL DATA COMMUNICATION LINKS May 2, 1995 Abandoned
08/432796 SYSTEM AND METHOD FOR AUTOMATICALLY DETERMINING TEST POINT FOR DC PARAMETRIC TEST May 1, 1995 Abandoned
Array ( [id] => 3750525 [patent_doc_number] => 05699512 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-16 [patent_title] => 'Software analysis protection method for changing the software pattern on the memory of a user terminal' [patent_app_type] => 1 [patent_app_number] => 8/431305 [patent_app_country] => US [patent_app_date] => 1995-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4319 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/699/05699512.pdf [firstpage_image] =>[orig_patent_app_number] => 431305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/431305
Software analysis protection method for changing the software pattern on the memory of a user terminal Apr 27, 1995 Issued
08/430651 DUAL MODE MEMORY FOR IC TERMINALS Apr 27, 1995 Abandoned
Array ( [id] => 3563801 [patent_doc_number] => 05574731 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-11-12 [patent_title] => 'Set/reset scan flip-flops' [patent_app_type] => 1 [patent_app_number] => 8/429944 [patent_app_country] => US [patent_app_date] => 1995-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 15 [patent_no_of_words] => 1819 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/574/05574731.pdf [firstpage_image] =>[orig_patent_app_number] => 429944 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/429944
Set/reset scan flip-flops Apr 26, 1995 Issued
08/429258 COPY PROTECTION CIRCUIT FOR A DATA IN A MEMORY Apr 24, 1995 Abandoned
08/421411 RECOVERY UNIT FOR MIRRORED PROCESSORS Apr 13, 1995 Abandoned
Array ( [id] => 3841159 [patent_doc_number] => 05784551 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-21 [patent_title] => 'Duplicate control and processing unit for telecommunications equipment' [patent_app_type] => 1 [patent_app_number] => 8/411686 [patent_app_country] => US [patent_app_date] => 1995-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7646 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/784/05784551.pdf [firstpage_image] =>[orig_patent_app_number] => 411686 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/411686
Duplicate control and processing unit for telecommunications equipment Mar 29, 1995 Issued
08/408882 SEMICONDUCTOR DEVICE HAVING TEST CIRCUIT Mar 23, 1995 Abandoned
Array ( [id] => 3848746 [patent_doc_number] => 05761405 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-02 [patent_title] => 'Data integrity guarantee system' [patent_app_type] => 1 [patent_app_number] => 8/407241 [patent_app_country] => US [patent_app_date] => 1995-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 9190 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 607 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/761/05761405.pdf [firstpage_image] =>[orig_patent_app_number] => 407241 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/407241
Data integrity guarantee system Mar 19, 1995 Issued
08/403607 SCAN TESTING DIGITAL LOGIC WITH DIFFERING FREQUENCIES OF SYSTEM CLOCK AND TEST CLOCK Mar 13, 1995 Abandoned
Array ( [id] => 3554524 [patent_doc_number] => 05555270 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-10 [patent_title] => 'Method and apparatus for constructing unique input/output sequence (UIO) sets utilizing transition distinctness measurements' [patent_app_type] => 1 [patent_app_number] => 8/403332 [patent_app_country] => US [patent_app_date] => 1995-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 19378 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 513 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/555/05555270.pdf [firstpage_image] =>[orig_patent_app_number] => 403332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/403332
Method and apparatus for constructing unique input/output sequence (UIO) sets utilizing transition distinctness measurements Mar 12, 1995 Issued
Array ( [id] => 3593027 [patent_doc_number] => 05581567 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-12-03 [patent_title] => 'Dual level error detection and correction employing data subsets from previously corrected data' [patent_app_type] => 1 [patent_app_number] => 8/401297 [patent_app_country] => US [patent_app_date] => 1995-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 7314 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/581/05581567.pdf [firstpage_image] =>[orig_patent_app_number] => 401297 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/401297
Dual level error detection and correction employing data subsets from previously corrected data Mar 8, 1995 Issued
08/399775 COMPUTER SERVER WITH IMPROVED RELIABILITY, AVAILABILITY AND SERVICEABILITY Mar 6, 1995 Abandoned
Array ( [id] => 3740161 [patent_doc_number] => 05703885 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-12-30 [patent_title] => 'Method and apparatus for constructing verification test sequences by merging and touring hierarchical unique input/output sequence (UIO) based test subsequence graphs' [patent_app_type] => 1 [patent_app_number] => 8/399008 [patent_app_country] => US [patent_app_date] => 1995-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 19382 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 638 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/703/05703885.pdf [firstpage_image] =>[orig_patent_app_number] => 399008 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/399008
Method and apparatus for constructing verification test sequences by merging and touring hierarchical unique input/output sequence (UIO) based test subsequence graphs Mar 5, 1995 Issued
Array ( [id] => 3990624 [patent_doc_number] => 06004027 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-21 [patent_title] => 'Method and apparatus for constructing test subsequence graphs utilizing unique input/output sequence (UIO) sets' [patent_app_type] => 1 [patent_app_number] => 8/399020 [patent_app_country] => US [patent_app_date] => 1995-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 41 [patent_no_of_words] => 19220 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 697 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/004/06004027.pdf [firstpage_image] =>[orig_patent_app_number] => 399020 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/399020
Method and apparatus for constructing test subsequence graphs utilizing unique input/output sequence (UIO) sets Mar 5, 1995 Issued
08/398400 EQUALIZATION AND DECODING FOR DIGITAL COMMUNICATION CHANNEL Mar 2, 1995 Abandoned
08/378871 METHOD OF CORRECTING READ ERROR IN DIGITAL DATA PROCESSING SYSTEM BY IMPLEMENTING A PREDETERMINED NUMBER OF DATA READ RETRIALS Jan 23, 1995 Abandoned
08/372704 ABBREVIATED TRIAL-AND-ERROR TECHNIQUE FOR CORRECTING LONG BURSTS OF CONSECUTIVE ERRORS WITHOUT REQUIRING A POINTER Jan 12, 1995 Abandoned
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