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Saumit Shah

Examiner (ID: 16826, Phone: (571)272-6959 , Office: P/2414 )

Most Active Art Unit
2414
Art Unit(s)
2414
Total Applications
605
Issued Applications
465
Pending Applications
88
Abandoned Applications
66

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3557836 [patent_doc_number] => 05548441 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Illumination system and method for a high definition light microscope' [patent_app_type] => 1 [patent_app_number] => 8/029641 [patent_app_country] => US [patent_app_date] => 1993-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 27 [patent_no_of_words] => 10422 [patent_no_of_claims] => 53 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548441.pdf [firstpage_image] =>[orig_patent_app_number] => 029641 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/029641
Illumination system and method for a high definition light microscope Mar 10, 1993 Issued
08/016445 INDICATION OF COVERAGE AREA LIMITS WITHIN DIGITAL COMMUNICATIONS SYSTEMS Feb 10, 1993 Abandoned
Array ( [id] => 3020970 [patent_doc_number] => 05333139 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-07-26 [patent_title] => 'Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain' [patent_app_type] => 1 [patent_app_number] => 7/998545 [patent_app_country] => US [patent_app_date] => 1992-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5830 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 159 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/333/05333139.pdf [firstpage_image] =>[orig_patent_app_number] => 998545 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/998545
Method of determining the number of individual integrated circuit computer chips or the like in a boundary scan test chain and the length of the chain Dec 29, 1992 Issued
07/995803 MEMORY SYSTEM Dec 22, 1992 Abandoned
07/987153 WATCHDOG TIMER CIRCUIT HAVING SOURCES FOR GENERATING RESET SIGNALS FOR RESETTING A WATCHDOG TIMER AND DATA PROCESSING UNIT HAVING THE WATCHDOG TIMER CIRCUIT Dec 7, 1992 Abandoned
Array ( [id] => 3811168 [patent_doc_number] => 05781715 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-07-14 [patent_title] => 'Fault-tolerant bridge/router with a distributed switch-over mechanism' [patent_app_type] => 1 [patent_app_number] => 7/958418 [patent_app_country] => US [patent_app_date] => 1992-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 3882 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/781/05781715.pdf [firstpage_image] =>[orig_patent_app_number] => 958418 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/958418
Fault-tolerant bridge/router with a distributed switch-over mechanism Oct 12, 1992 Issued
Array ( [id] => 3125609 [patent_doc_number] => 05396501 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-03-07 [patent_title] => 'Test access port controller with a gate for controlling a shift data register signal' [patent_app_type] => 1 [patent_app_number] => 7/954745 [patent_app_country] => US [patent_app_date] => 1992-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 1618 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/396/05396501.pdf [firstpage_image] =>[orig_patent_app_number] => 954745 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/954745
Test access port controller with a gate for controlling a shift data register signal Sep 29, 1992 Issued
Array ( [id] => 3849048 [patent_doc_number] => 05815656 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-09-29 [patent_title] => 'Method of validating memory structures in data processing systems' [patent_app_type] => 1 [patent_app_number] => 7/949668 [patent_app_country] => US [patent_app_date] => 1992-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6038 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/815/05815656.pdf [firstpage_image] =>[orig_patent_app_number] => 949668 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/949668
Method of validating memory structures in data processing systems Sep 22, 1992 Issued
Array ( [id] => 3577612 [patent_doc_number] => 05485468 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-01-16 [patent_title] => 'Data output encoder having resetting mechanism' [patent_app_type] => 1 [patent_app_number] => 7/943548 [patent_app_country] => US [patent_app_date] => 1992-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 4352 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/485/05485468.pdf [firstpage_image] =>[orig_patent_app_number] => 943548 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/943548
Data output encoder having resetting mechanism Sep 10, 1992 Issued
Array ( [id] => 3117986 [patent_doc_number] => 05448720 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-09-05 [patent_title] => 'Information processing system for obtaining status data of a simplex system by a standby system of a duplex system' [patent_app_type] => 1 [patent_app_number] => 7/940248 [patent_app_country] => US [patent_app_date] => 1992-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4439 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/448/05448720.pdf [firstpage_image] =>[orig_patent_app_number] => 940248 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/940248
Information processing system for obtaining status data of a simplex system by a standby system of a duplex system Sep 3, 1992 Issued
Array ( [id] => 3021290 [patent_doc_number] => 05355471 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-10-11 [patent_title] => 'Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort' [patent_app_type] => 1 [patent_app_number] => 7/929370 [patent_app_country] => US [patent_app_date] => 1992-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4362 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/355/05355471.pdf [firstpage_image] =>[orig_patent_app_number] => 929370 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/929370
Multiprocessor cache coherency tester that exercises the coherency logic exhaustively and also detects errors in a processor using an automatic CPU sort Aug 13, 1992 Issued
07/914570 METHOD OF CORRECTING READ ERROR IN DIGITAL DATA PROCESSING SYSTEM BY IMPLEMENTING A PREDETERMINED NUMBER OF DATA READ RETRIALS Jul 16, 1992 Abandoned
07/905540 METHOD AND APPARATUS FOR 10BASE-T ETHERNET POLARITY DETECTION AND CORRECTION Jun 28, 1992 Abandoned
07/905390 AN APPARATUS FOR DETECTING THE PRESENCE OF INFORMATION DATA STORED IN A RECORDING MEDIUM TO DETERMINE IF NEW DATA CAN BE WRITTEN TO THAT RECORDING MEDIUM Jun 28, 1992 Abandoned
07/896960 SOLID-STATE DISK MEMORY USING STORAGE DEVICES WITH DEFECTS Jun 10, 1992 Abandoned
Array ( [id] => 3104352 [patent_doc_number] => 05313464 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-05-17 [patent_title] => 'Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols' [patent_app_type] => 1 [patent_app_number] => 7/878749 [patent_app_country] => US [patent_app_date] => 1992-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3638 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/313/05313464.pdf [firstpage_image] =>[orig_patent_app_number] => 878749 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/878749
Fault tolerant memory using bus bit aligned Reed-Solomon error correction code symbols May 4, 1992 Issued
07/862932 METHOD AND SYSTEM FOR SYSTEM DEBUGGING THROUGH A KEYBOARD DEVICE DRIVER Apr 2, 1992 Abandoned
Array ( [id] => 3085150 [patent_doc_number] => 05365528 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1994-11-15 [patent_title] => 'Method for testing delay faults in non-scan sequential circuits' [patent_app_type] => 1 [patent_app_number] => 7/862942 [patent_app_country] => US [patent_app_date] => 1992-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 4731 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 388 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/365/05365528.pdf [firstpage_image] =>[orig_patent_app_number] => 862942 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/862942
Method for testing delay faults in non-scan sequential circuits Apr 2, 1992 Issued
Array ( [id] => 3826848 [patent_doc_number] => 05771245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-06-23 [patent_title] => 'Process for independently protecting two dimensional codes from one or more burst errors patterns' [patent_app_type] => 1 [patent_app_number] => 7/856001 [patent_app_country] => US [patent_app_date] => 1992-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 18 [patent_no_of_words] => 5608 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 24 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/771/05771245.pdf [firstpage_image] =>[orig_patent_app_number] => 856001 [rel_patent_id] =>[rel_patent_doc_number] =>)
07/856001
Process for independently protecting two dimensional codes from one or more burst errors patterns Mar 19, 1992 Issued
07/845973 FAULT-TOLERANT MULTIPLE PROCESSOR SYSTEM WITH SIGNATURE VOTING Mar 3, 1992 Abandoned
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