Search

Savitri Mulpuri

Examiner (ID: 434, Phone: (571)272-1677 , Office: P/2816 )

Most Active Art Unit
2812
Art Unit(s)
2816, 1107, 2812
Total Applications
1898
Issued Applications
1575
Pending Applications
50
Abandoned Applications
278

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1568388 [patent_doc_number] => 06376880 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-23 [patent_title] => 'High-speed lateral bipolar device in SOI process' [patent_app_type] => B1 [patent_app_number] => 09/406451 [patent_app_country] => US [patent_app_date] => 1999-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 4930 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/376/06376880.pdf [firstpage_image] =>[orig_patent_app_number] => 09406451 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/406451
High-speed lateral bipolar device in SOI process Sep 26, 1999 Issued
Array ( [id] => 4331739 [patent_doc_number] => 06329698 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Forming a self-aligned epitaxial base bipolar transistor' [patent_app_type] => 1 [patent_app_number] => 9/399911 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5722 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329698.pdf [firstpage_image] =>[orig_patent_app_number] => 399911 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/399911
Forming a self-aligned epitaxial base bipolar transistor Sep 20, 1999 Issued
Array ( [id] => 1583070 [patent_doc_number] => 06424036 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Semiconductor device and method for manufacturing the same' [patent_app_type] => B1 [patent_app_number] => 09/398161 [patent_app_country] => US [patent_app_date] => 1999-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 5890 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 293 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/424/06424036.pdf [firstpage_image] =>[orig_patent_app_number] => 09398161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398161
Semiconductor device and method for manufacturing the same Sep 15, 1999 Issued
Array ( [id] => 7063428 [patent_doc_number] => 20010042880 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'DRAM CELL WITH ACTIVE AREA RECLAIM' [patent_app_type] => new [patent_app_number] => 09/396932 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3437 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042880.pdf [firstpage_image] =>[orig_patent_app_number] => 09396932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396932
DRAM CELL WITH ACTIVE AREA RECLAIM Sep 14, 1999 Abandoned
Array ( [id] => 4301409 [patent_doc_number] => 06184580 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-06 [patent_title] => 'Ball grid array package with conductive leads' [patent_app_type] => 1 [patent_app_number] => 9/394263 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 3675 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 316 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/184/06184580.pdf [firstpage_image] =>[orig_patent_app_number] => 394263 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394263
Ball grid array package with conductive leads Sep 9, 1999 Issued
Array ( [id] => 4299797 [patent_doc_number] => 06180977 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash' [patent_app_type] => 1 [patent_app_number] => 9/389631 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2903 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/180/06180977.pdf [firstpage_image] =>[orig_patent_app_number] => 389631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389631
Self-aligned edge implanted cell to reduce leakage current and improve program speed in split-gate flash Sep 2, 1999 Issued
Array ( [id] => 1391590 [patent_doc_number] => 06552414 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-22 [patent_title] => 'Semiconductor device with selectively diffused regions' [patent_app_type] => B1 [patent_app_number] => 09/331932 [patent_app_country] => US [patent_app_date] => 1999-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 16 [patent_no_of_words] => 6050 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/552/06552414.pdf [firstpage_image] =>[orig_patent_app_number] => 09331932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/331932
Semiconductor device with selectively diffused regions Aug 26, 1999 Issued
Array ( [id] => 4385452 [patent_doc_number] => 06303959 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Semiconductor device having reduced source leakage during source erase' [patent_app_type] => 1 [patent_app_number] => 9/375751 [patent_app_country] => US [patent_app_date] => 1999-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 5128 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303959.pdf [firstpage_image] =>[orig_patent_app_number] => 375751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/375751
Semiconductor device having reduced source leakage during source erase Aug 24, 1999 Issued
Array ( [id] => 4358689 [patent_doc_number] => 06291845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Fully-dielectric-isolated FET technology' [patent_app_type] => 1 [patent_app_number] => 9/382403 [patent_app_country] => US [patent_app_date] => 1999-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 4709 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291845.pdf [firstpage_image] =>[orig_patent_app_number] => 382403 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/382403
Fully-dielectric-isolated FET technology Aug 23, 1999 Issued
Array ( [id] => 4222691 [patent_doc_number] => 06087695 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Source side injection flash EEPROM memory cell with dielectric pillar and operation' [patent_app_type] => 1 [patent_app_number] => 9/378271 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2099 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087695.pdf [firstpage_image] =>[orig_patent_app_number] => 378271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378271
Source side injection flash EEPROM memory cell with dielectric pillar and operation Aug 19, 1999 Issued
Array ( [id] => 4358661 [patent_doc_number] => 06291843 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Semiconductor memory device' [patent_app_type] => 1 [patent_app_number] => 9/376362 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4250 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/291/06291843.pdf [firstpage_image] =>[orig_patent_app_number] => 376362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376362
Semiconductor memory device Aug 17, 1999 Issued
Array ( [id] => 7623536 [patent_doc_number] => 06686629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-02-03 [patent_title] => 'SOI MOSFETS exhibiting reduced floating-body effects' [patent_app_type] => B1 [patent_app_number] => 09/377331 [patent_app_country] => US [patent_app_date] => 1999-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3317 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 10 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686629.pdf [firstpage_image] =>[orig_patent_app_number] => 09377331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377331
SOI MOSFETS exhibiting reduced floating-body effects Aug 17, 1999 Issued
Array ( [id] => 4355172 [patent_doc_number] => 06215149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Trenched gate semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/376762 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2937 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215149.pdf [firstpage_image] =>[orig_patent_app_number] => 376762 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376762
Trenched gate semiconductor device Aug 16, 1999 Issued
Array ( [id] => 4310189 [patent_doc_number] => 06252279 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'DMOS transistor having a high reliability and a method for fabricating the same' [patent_app_type] => 1 [patent_app_number] => 9/376710 [patent_app_country] => US [patent_app_date] => 1999-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3850 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/252/06252279.pdf [firstpage_image] =>[orig_patent_app_number] => 376710 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376710
DMOS transistor having a high reliability and a method for fabricating the same Aug 16, 1999 Issued
Array ( [id] => 4360386 [patent_doc_number] => 06218690 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Transistor having reverse self-aligned structure' [patent_app_type] => 1 [patent_app_number] => 9/376041 [patent_app_country] => US [patent_app_date] => 1999-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2634 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218690.pdf [firstpage_image] =>[orig_patent_app_number] => 376041 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/376041
Transistor having reverse self-aligned structure Aug 15, 1999 Issued
Array ( [id] => 1590867 [patent_doc_number] => 06483171 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same' [patent_app_type] => B1 [patent_app_number] => 09/386313 [patent_app_country] => US [patent_app_date] => 1999-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 2275 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/483/06483171.pdf [firstpage_image] =>[orig_patent_app_number] => 09386313 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386313
Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same Aug 12, 1999 Issued
Array ( [id] => 4324564 [patent_doc_number] => 06249016 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Integrated circuit capacitor including tapered plug' [patent_app_type] => 1 [patent_app_number] => 9/364603 [patent_app_country] => US [patent_app_date] => 1999-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2994 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249016.pdf [firstpage_image] =>[orig_patent_app_number] => 364603 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/364603
Integrated circuit capacitor including tapered plug Jul 29, 1999 Issued
Array ( [id] => 1171944 [patent_doc_number] => 06753568 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-22 [patent_title] => 'Memory device' [patent_app_type] => B1 [patent_app_number] => 09/362200 [patent_app_country] => US [patent_app_date] => 1999-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 58 [patent_no_of_words] => 13286 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/753/06753568.pdf [firstpage_image] =>[orig_patent_app_number] => 09362200 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/362200
Memory device Jul 27, 1999 Issued
Array ( [id] => 4355420 [patent_doc_number] => 06215164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Elevated image sensor array which includes isolation between uniquely shaped image sensors' [patent_app_type] => 1 [patent_app_number] => 9/361342 [patent_app_country] => US [patent_app_date] => 1999-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3728 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/215/06215164.pdf [firstpage_image] =>[orig_patent_app_number] => 361342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/361342
Elevated image sensor array which includes isolation between uniquely shaped image sensors Jul 25, 1999 Issued
Array ( [id] => 7645260 [patent_doc_number] => 06472712 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Semiconductor device with reduced transistor leakage current' [patent_app_type] => B1 [patent_app_number] => 09/357922 [patent_app_country] => US [patent_app_date] => 1999-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4329 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472712.pdf [firstpage_image] =>[orig_patent_app_number] => 09357922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/357922
Semiconductor device with reduced transistor leakage current Jul 20, 1999 Issued
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