![](/images/general/no_picture/200_user.png)
Scott A Browne
Examiner (ID: 918, Phone: (571)270-0151 , Office: P/3617 )
Most Active Art Unit | 3617 |
Art Unit(s) | 3617, 4128 |
Total Applications | 562 |
Issued Applications | 347 |
Pending Applications | 76 |
Abandoned Applications | 126 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 17181369
[patent_doc_number] => 11158618
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-10-26
[patent_title] => Light conversion device
[patent_app_type] => utility
[patent_app_number] => 16/657574
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5612
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 269
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657574
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657574 | Light conversion device | Oct 17, 2019 | Issued |
Array
(
[id] => 17254048
[patent_doc_number] => 11189546
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-11-30
[patent_title] => Semiconductor arrangement and method for making
[patent_app_type] => utility
[patent_app_number] => 16/656986
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 12
[patent_no_of_words] => 6629
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 42
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656986
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/656986 | Semiconductor arrangement and method for making | Oct 17, 2019 | Issued |
Array
(
[id] => 16781820
[patent_doc_number] => 20210118899
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => Memory Arrays And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells
[patent_app_type] => utility
[patent_app_number] => 16/657498
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6822
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657498
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657498 | Memory arrays and methods used in forming a memory array comprising strings of memory cells | Oct 17, 2019 | Issued |
Array
(
[id] => 16781916
[patent_doc_number] => 20210118995
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => GATE STRUCTURES FOR SEMICONDUCTOR DEVICES
[patent_app_type] => utility
[patent_app_number] => 16/657017
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14772
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16657017
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/657017 | Gate structures for semiconductor devices | Oct 17, 2019 | Issued |
Array
(
[id] => 16781751
[patent_doc_number] => 20210118830
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => SEMICONDUCTOR DEVICE WITH SPACER OVER SIDEWALL OF BONDING PAD AND METHOD FOR PREPARING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/656823
[patent_app_country] => US
[patent_app_date] => 2019-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 8544
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656823
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/656823 | Semiconductor device with spacer over sidewall of bonding pad and method for preparing the same | Oct 17, 2019 | Issued |
Array
(
[id] => 17310176
[patent_doc_number] => 11211302
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-28
[patent_title] => Semiconductor device package
[patent_app_type] => utility
[patent_app_number] => 16/656338
[patent_app_country] => US
[patent_app_date] => 2019-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 39
[patent_no_of_words] => 7956
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656338
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/656338 | Semiconductor device package | Oct 16, 2019 | Issued |
Array
(
[id] => 17326455
[patent_doc_number] => 11217480
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-01-04
[patent_title] => Semiconductor structure with a laminated layer
[patent_app_type] => utility
[patent_app_number] => 16/656384
[patent_app_country] => US
[patent_app_date] => 2019-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 32
[patent_no_of_words] => 12823
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 153
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16656384
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/656384 | Semiconductor structure with a laminated layer | Oct 16, 2019 | Issued |
Array
(
[id] => 15442797
[patent_doc_number] => 20200035582
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-30
[patent_title] => SEMICONDUCTOR DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/592213
[patent_app_country] => US
[patent_app_date] => 2019-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5758
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16592213
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/592213 | Semiconductor device | Oct 2, 2019 | Issued |
Array
(
[id] => 15415287
[patent_doc_number] => 20200027966
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-01-23
[patent_title] => SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF
[patent_app_type] => utility
[patent_app_number] => 16/584516
[patent_app_country] => US
[patent_app_date] => 2019-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10090
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -7
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16584516
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/584516 | SEMICONDUCTOR DEVICE AND MANUFACTURE THEREOF | Sep 25, 2019 | Abandoned |
Array
(
[id] => 16865892
[patent_doc_number] => 11024645
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-01
[patent_title] => Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same
[patent_app_type] => utility
[patent_app_number] => 16/583906
[patent_app_country] => US
[patent_app_date] => 2019-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 26
[patent_figures_cnt] => 36
[patent_no_of_words] => 16635
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583906
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/583906 | Three-dimensional memory device containing a silicon nitride ring in an opening in a memory film and method of making the same | Sep 25, 2019 | Issued |
Array
(
[id] => 16896462
[patent_doc_number] => 11038025
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-06-15
[patent_title] => HEMT-compatible lateral rectifier structure
[patent_app_type] => utility
[patent_app_number] => 16/562918
[patent_app_country] => US
[patent_app_date] => 2019-09-06
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 19
[patent_no_of_words] => 5311
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 89
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562918
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/562918 | HEMT-compatible lateral rectifier structure | Sep 5, 2019 | Issued |
Array
(
[id] => 15300185
[patent_doc_number] => 20190393228
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-12-26
[patent_title] => SRAM CELL WORD LINE STRUCTURE WITH REDUCED RC EFFECTS
[patent_app_type] => utility
[patent_app_number] => 16/562299
[patent_app_country] => US
[patent_app_date] => 2019-09-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7459
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16562299
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/562299 | SRAM cell word line structure with reduced RC effects | Sep 4, 2019 | Issued |
Array
(
[id] => 16617346
[patent_doc_number] => 20210035999
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/556919
[patent_app_country] => US
[patent_app_date] => 2019-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556919
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/556919 | Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same | Aug 29, 2019 | Issued |
Array
(
[id] => 16617345
[patent_doc_number] => 20210035998
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE HAVING ENHANCED CONTACT BETWEEN POLYCRYSTALLINE CHANNEL AND EPITAXIAL PEDESTAL STRUCTURE AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/556854
[patent_app_country] => US
[patent_app_date] => 2019-08-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 20373
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16556854
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/556854 | Three-dimensional memory device having enhanced contact between polycrystalline channel and epitaxial pedestal structure and method of making the same | Aug 29, 2019 | Issued |
Array
(
[id] => 16516220
[patent_doc_number] => 20200395478
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-12-17
[patent_title] => METHOD OF FORMING A SEMICONDUCTOR DEVICE AND STRUCTURE THEREFOR
[patent_app_type] => utility
[patent_app_number] => 16/545622
[patent_app_country] => US
[patent_app_date] => 2019-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7268
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 123
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16545622
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/545622 | Method of forming a semiconductor device and structure therefor | Aug 19, 2019 | Issued |
Array
(
[id] => 17270504
[patent_doc_number] => 11195935
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-12-07
[patent_title] => Semiconductor device with novel spacer structures having novel configurations
[patent_app_type] => utility
[patent_app_number] => 16/531617
[patent_app_country] => US
[patent_app_date] => 2019-08-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 12
[patent_no_of_words] => 10938
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 212
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16531617
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/531617 | Semiconductor device with novel spacer structures having novel configurations | Aug 4, 2019 | Issued |
Array
(
[id] => 15462605
[patent_doc_number] => 20200044127
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-02-06
[patent_title] => MICRO LED STRUCTURE AND METHOD OF MANUFACTURING SAME
[patent_app_type] => utility
[patent_app_number] => 16/526702
[patent_app_country] => US
[patent_app_date] => 2019-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7680
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -1
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526702
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/526702 | Micro LED structure and method of manufacturing same | Jul 29, 2019 | Issued |
Array
(
[id] => 16789191
[patent_doc_number] => 10991630
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Semiconductor device and method
[patent_app_type] => utility
[patent_app_number] => 16/526163
[patent_app_country] => US
[patent_app_date] => 2019-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 30
[patent_no_of_words] => 9744
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 130
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526163
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/526163 | Semiconductor device and method | Jul 29, 2019 | Issued |
Array
(
[id] => 16617350
[patent_doc_number] => 20210036003
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-02-04
[patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING A VERTICAL SEMICONDUCTOR CHANNEL CONTAINING A CONNECTION STRAP AND METHOD OF MAKING THE SAME
[patent_app_type] => utility
[patent_app_number] => 16/526128
[patent_app_country] => US
[patent_app_date] => 2019-07-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17408
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -12
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16526128
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/526128 | Three-dimensional memory device containing a vertical semiconductor channel containing a connection strap and method of making the same | Jul 29, 2019 | Issued |
Array
(
[id] => 16081493
[patent_doc_number] => 20200194733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2020-06-18
[patent_title] => METHOD FOR PREPARING DISPLAY PANEL, DISPLAY PANEL AND DISPLAY DEVICE
[patent_app_type] => utility
[patent_app_number] => 16/523410
[patent_app_country] => US
[patent_app_date] => 2019-07-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4764
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 67
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16523410
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/523410 | Method for preparing display panel, display panel and display device | Jul 25, 2019 | Issued |