
Scott A. Smith
Examiner (ID: 5262, Phone: (571)272-4469 , Office: P/3721 )
| Most Active Art Unit | 3721 |
| Art Unit(s) | 3731, 3204, 3727, 3721, 3616, 3205 |
| Total Applications | 3908 |
| Issued Applications | 3490 |
| Pending Applications | 118 |
| Abandoned Applications | 330 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 919713
[patent_doc_number] => 07324373
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-01-29
[patent_title] => 'Semiconductor device and short circuit detecting method'
[patent_app_type] => utility
[patent_app_number] => 11/259141
[patent_app_country] => US
[patent_app_date] => 2005-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 33
[patent_no_of_words] => 11229
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 125
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/324/07324373.pdf
[firstpage_image] =>[orig_patent_app_number] => 11259141
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/259141 | Semiconductor device and short circuit detecting method | Oct 26, 2005 | Issued |
Array
(
[id] => 682538
[patent_doc_number] => 07085188
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-08-01
[patent_title] => 'Semiconductor memory device, control method thereof, and control method of semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/255969
[patent_app_country] => US
[patent_app_date] => 2005-10-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 13607
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/085/07085188.pdf
[firstpage_image] =>[orig_patent_app_number] => 11255969
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/255969 | Semiconductor memory device, control method thereof, and control method of semiconductor device | Oct 23, 2005 | Issued |
Array
(
[id] => 5709212
[patent_doc_number] => 20060050557
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'Nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/251963
[patent_app_country] => US
[patent_app_date] => 2005-10-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
[patent_figures_cnt] => 28
[patent_no_of_words] => 12829
[patent_no_of_claims] => 9
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0050/20060050557.pdf
[firstpage_image] =>[orig_patent_app_number] => 11251963
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/251963 | Nonvolatile semiconductor memory device | Oct 17, 2005 | Issued |
Array
(
[id] => 441361
[patent_doc_number] => 07260018
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-08-21
[patent_title] => 'Multiport semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/250407
[patent_app_country] => US
[patent_app_date] => 2005-10-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 8989
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 321
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/260/07260018.pdf
[firstpage_image] =>[orig_patent_app_number] => 11250407
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/250407 | Multiport semiconductor memory device | Oct 16, 2005 | Issued |
Array
(
[id] => 433611
[patent_doc_number] => 07266016
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-09-04
[patent_title] => 'Electrically rewritable nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/246215
[patent_app_country] => US
[patent_app_date] => 2005-10-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4961
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 188
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/266/07266016.pdf
[firstpage_image] =>[orig_patent_app_number] => 11246215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/246215 | Electrically rewritable nonvolatile semiconductor memory device | Oct 10, 2005 | Issued |
Array
(
[id] => 512262
[patent_doc_number] => 07203117
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => utility
[patent_app_number] => 11/245075
[patent_app_country] => US
[patent_app_date] => 2005-10-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 5
[patent_no_of_words] => 2800
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 168
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203117.pdf
[firstpage_image] =>[orig_patent_app_number] => 11245075
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/245075 | Semiconductor integrated circuit | Oct 6, 2005 | Issued |
Array
(
[id] => 5806332
[patent_doc_number] => 20060092685
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-04
[patent_title] => 'Storage apparatus'
[patent_app_type] => utility
[patent_app_number] => 11/245325
[patent_app_country] => US
[patent_app_date] => 2005-10-05
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 7580
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0092/20060092685.pdf
[firstpage_image] =>[orig_patent_app_number] => 11245325
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/245325 | Storage apparatus | Oct 4, 2005 | Issued |
Array
(
[id] => 556769
[patent_doc_number] => 07170769
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-01-30
[patent_title] => 'High performance and reduced area architecture for a fully parallel search of a TCAM cell'
[patent_app_type] => utility
[patent_app_number] => 11/242183
[patent_app_country] => US
[patent_app_date] => 2005-10-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5745
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 263
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/170/07170769.pdf
[firstpage_image] =>[orig_patent_app_number] => 11242183
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/242183 | High performance and reduced area architecture for a fully parallel search of a TCAM cell | Oct 2, 2005 | Issued |
Array
(
[id] => 527912
[patent_doc_number] => 07190605
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-03-13
[patent_title] => 'Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells'
[patent_app_type] => utility
[patent_app_number] => 11/240659
[patent_app_country] => US
[patent_app_date] => 2005-09-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 7506
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 161
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/190/07190605.pdf
[firstpage_image] =>[orig_patent_app_number] => 11240659
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/240659 | Semiconductor memory and method for operating a semiconductor memory comprising a plurality of memory cells | Sep 29, 2005 | Issued |
Array
(
[id] => 5819194
[patent_doc_number] => 20060023507
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-02-02
[patent_title] => 'Method of reducing disturbs in non-volatile memory'
[patent_app_type] => utility
[patent_app_number] => 11/238911
[patent_app_country] => US
[patent_app_date] => 2005-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 8146
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0023/20060023507.pdf
[firstpage_image] =>[orig_patent_app_number] => 11238911
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/238911 | Method of reducing disturbs in non-volatile memory | Sep 27, 2005 | Issued |
Array
(
[id] => 5886321
[patent_doc_number] => 20060274591
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-12-07
[patent_title] => 'Semiconductor memory device and information processing system'
[patent_app_type] => utility
[patent_app_number] => 11/236739
[patent_app_country] => US
[patent_app_date] => 2005-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 10210
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0274/20060274591.pdf
[firstpage_image] =>[orig_patent_app_number] => 11236739
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/236739 | Semiconductor memory device and information processing system | Sep 27, 2005 | Issued |
Array
(
[id] => 635970
[patent_doc_number] => 07130221
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-31
[patent_title] => 'Dual gate multi-bit semiconductor memory'
[patent_app_type] => utility
[patent_app_number] => 11/234983
[patent_app_country] => US
[patent_app_date] => 2005-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 3796
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 262
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/130/07130221.pdf
[firstpage_image] =>[orig_patent_app_number] => 11234983
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234983 | Dual gate multi-bit semiconductor memory | Sep 25, 2005 | Issued |
Array
(
[id] => 635971
[patent_doc_number] => 07130222
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-10-31
[patent_title] => 'Nonvolatile memory with program while program verify'
[patent_app_type] => utility
[patent_app_number] => 11/235881
[patent_app_country] => US
[patent_app_date] => 2005-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 6834
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/130/07130222.pdf
[firstpage_image] =>[orig_patent_app_number] => 11235881
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/235881 | Nonvolatile memory with program while program verify | Sep 25, 2005 | Issued |
Array
(
[id] => 4459044
[patent_doc_number] => 07894291
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-02-22
[patent_title] => 'Circuit and method for controlling a standby voltage level of a memory'
[patent_app_type] => utility
[patent_app_number] => 11/162847
[patent_app_country] => US
[patent_app_date] => 2005-09-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 4504
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 102
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/894/07894291.pdf
[firstpage_image] =>[orig_patent_app_number] => 11162847
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/162847 | Circuit and method for controlling a standby voltage level of a memory | Sep 25, 2005 | Issued |
Array
(
[id] => 912745
[patent_doc_number] => 07330388
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2008-02-12
[patent_title] => 'Sense amplifier circuit and method of operation'
[patent_app_type] => utility
[patent_app_number] => 11/234411
[patent_app_country] => US
[patent_app_date] => 2005-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 16
[patent_no_of_words] => 5570
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/330/07330388.pdf
[firstpage_image] =>[orig_patent_app_number] => 11234411
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/234411 | Sense amplifier circuit and method of operation | Sep 22, 2005 | Issued |
Array
(
[id] => 5825339
[patent_doc_number] => 20060062042
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-23
[patent_title] => 'Read method and sensing device'
[patent_app_type] => utility
[patent_app_number] => 11/231895
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 6039
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0062/20060062042.pdf
[firstpage_image] =>[orig_patent_app_number] => 11231895
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/231895 | Read method and sensing device | Sep 21, 2005 | Issued |
Array
(
[id] => 490034
[patent_doc_number] => 07218543
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-05-15
[patent_title] => 'ROM load balancing for bit lines'
[patent_app_type] => utility
[patent_app_number] => 11/232767
[patent_app_country] => US
[patent_app_date] => 2005-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 21
[patent_no_of_words] => 7649
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 72
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/218/07218543.pdf
[firstpage_image] =>[orig_patent_app_number] => 11232767
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/232767 | ROM load balancing for bit lines | Sep 21, 2005 | Issued |
Array
(
[id] => 554543
[patent_doc_number] => 07167405
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-01-23
[patent_title] => 'Data transfer verification systems and methods'
[patent_app_type] => utility
[patent_app_number] => 11/230087
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 2686
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 92
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/167/07167405.pdf
[firstpage_image] =>[orig_patent_app_number] => 11230087
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/230087 | Data transfer verification systems and methods | Sep 18, 2005 | Issued |
Array
(
[id] => 512192
[patent_doc_number] => 07203108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-10
[patent_title] => 'Reliability test method for a ferroelectric memory device'
[patent_app_type] => utility
[patent_app_number] => 11/228317
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
[patent_figures_cnt] => 41
[patent_no_of_words] => 12740
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/203/07203108.pdf
[firstpage_image] =>[orig_patent_app_number] => 11228317
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/228317 | Reliability test method for a ferroelectric memory device | Sep 18, 2005 | Issued |
Array
(
[id] => 5636178
[patent_doc_number] => 20060067151
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-30
[patent_title] => 'Memory'
[patent_app_type] => utility
[patent_app_number] => 11/228215
[patent_app_country] => US
[patent_app_date] => 2005-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 7715
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0067/20060067151.pdf
[firstpage_image] =>[orig_patent_app_number] => 11228215
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/228215 | Memory | Sep 18, 2005 | Issued |