Scott A. Smith

Array ( [id] => 657305 [patent_doc_number] => 07110317 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-19 [patent_title] => 'SRAM employing virtual rail scheme stable against various process-voltage-temperature variations' [patent_app_type] => utility [patent_app_number] => 11/124787 [patent_app_country] => US [patent_app_date] => 2005-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3613 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/110/07110317.pdf [firstpage_image] =>[orig_patent_app_number] => 11124787 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547511 [patent_doc_number] => 07177198 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Compensated method to implement a high voltage discharge phase after erase pulse in a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/123979 [patent_app_country] => US [patent_app_date] => 2005-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1749 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177198.pdf [firstpage_image] =>[orig_patent_app_number] => 11123979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 704719 [patent_doc_number] => 07064992 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-20 [patent_title] => 'Method and apparatus for saving current in a memory device' [patent_app_type] => utility [patent_app_number] => 10/908283 [patent_app_country] => US [patent_app_date] => 2005-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4111 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/064/07064992.pdf [firstpage_image] =>[orig_patent_app_number] => 10908283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7044387 [patent_doc_number] => 20050248982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Method and circuit for verifying and eventually substituting defective reference cells of a memory' [patent_app_type] => utility [patent_app_number] => 11/121615 [patent_app_country] => US [patent_app_date] => 2005-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1966 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248982.pdf [firstpage_image] =>[orig_patent_app_number] => 11121615 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 437184 [patent_doc_number] => 07263023 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-28 [patent_title] => 'Semiconductor memory device having memory architecture supporting hyper-threading operation in host system' [patent_app_type] => utility [patent_app_number] => 11/119687 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7457 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/263/07263023.pdf [firstpage_image] =>[orig_patent_app_number] => 11119687 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 674415 [patent_doc_number] => 07092281 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-08-15 [patent_title] => 'Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activity' [patent_app_type] => utility [patent_app_number] => 11/116589 [patent_app_country] => US [patent_app_date] => 2005-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 7801 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092281.pdf [firstpage_image] =>[orig_patent_app_number] => 11116589 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5833422 [patent_doc_number] => 20060245252 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-02 [patent_title] => 'Flash memory programming to reduce program disturb' [patent_app_type] => utility [patent_app_number] => 11/115681 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3002 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0245/20060245252.pdf [firstpage_image] =>[orig_patent_app_number] => 11115681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 644122 [patent_doc_number] => 07123521 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-17 [patent_title] => 'Random cache read' [patent_app_type] => utility [patent_app_number] => 11/115489 [patent_app_country] => US [patent_app_date] => 2005-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4930 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/123/07123521.pdf [firstpage_image] =>[orig_patent_app_number] => 11115489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 665632 [patent_doc_number] => 07102960 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/114087 [patent_app_country] => US [patent_app_date] => 2005-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 14490 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102960.pdf [firstpage_image] =>[orig_patent_app_number] => 11114087 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 661120 [patent_doc_number] => 07106624 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Magnetic element utilizing spin transfer and an mram device using the magnetic element' [patent_app_type] => utility [patent_app_number] => 11/114946 [patent_app_country] => US [patent_app_date] => 2005-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6984 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106624.pdf [firstpage_image] =>[orig_patent_app_number] => 11114946 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7044386 [patent_doc_number] => 20050248981 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-10 [patent_title] => 'Magnetic storage element, recording method using the same, and magnetic storage device' [patent_app_type] => utility [patent_app_number] => 11/112374 [patent_app_country] => US [patent_app_date] => 2005-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12025 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0248/20050248981.pdf [firstpage_image] =>[orig_patent_app_number] => 11112374 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 661117 [patent_doc_number] => 07106623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Phase-change multi-level cell and operating method thereof' [patent_app_type] => utility [patent_app_number] => 10/907889 [patent_app_country] => US [patent_app_date] => 2005-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2225 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/106/07106623.pdf [firstpage_image] =>[orig_patent_app_number] => 10907889 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7068250 [patent_doc_number] => 20050243633 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Memory circuit and method for providing an item of information for a prescribed period of time' [patent_app_type] => utility [patent_app_number] => 11/109583 [patent_app_country] => US [patent_app_date] => 2005-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3494 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20050243633.pdf [firstpage_image] =>[orig_patent_app_number] => 11109583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 526338 [patent_doc_number] => 07193921 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Cascade wake-up circuit preventing power noise in memory device' [patent_app_type] => utility [patent_app_number] => 11/103047 [patent_app_country] => US [patent_app_date] => 2005-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4389 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/193/07193921.pdf [firstpage_image] =>[orig_patent_app_number] => 11103047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6911064 [patent_doc_number] => 20050174822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-08-11 [patent_title] => 'Bit line control circuit for a content addressable memory' [patent_app_type] => utility [patent_app_number] => 11/101873 [patent_app_country] => US [patent_app_date] => 2005-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5202 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0174/20050174822.pdf [firstpage_image] =>[orig_patent_app_number] => 11101873 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7068253 [patent_doc_number] => 20050243636 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-11-03 [patent_title] => 'Electronic memory apparatus, and method for deactivating redundant bit lines or word lines' [patent_app_type] => utility [patent_app_number] => 11/102071 [patent_app_country] => US [patent_app_date] => 2005-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3079 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0243/20050243636.pdf [firstpage_image] =>[orig_patent_app_number] => 11102071 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 517047 [patent_doc_number] => 07200027 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Ferroelectric memory reference generator systems using staging capacitors' [patent_app_type] => utility [patent_app_number] => 11/100013 [patent_app_country] => US [patent_app_date] => 2005-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 7773 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/200/07200027.pdf [firstpage_image] =>[orig_patent_app_number] => 11100013 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 665604 [patent_doc_number] => 07102947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/095883 [patent_app_country] => US [patent_app_date] => 2005-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 62 [patent_no_of_words] => 28126 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102947.pdf [firstpage_image] =>[orig_patent_app_number] => 11095883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 547275 [patent_doc_number] => 07177180 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-13 [patent_title] => 'Method and apparatus for reading data from a ferromagnetic memory cell' [patent_app_type] => utility [patent_app_number] => 11/089018 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3133 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/177/07177180.pdf [firstpage_image] =>[orig_patent_app_number] => 11089018 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 572969 [patent_doc_number] => 07158416 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-02 [patent_title] => 'Method for operating a flash memory device' [patent_app_type] => utility [patent_app_number] => 11/081085 [patent_app_country] => US [patent_app_date] => 2005-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1547 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/158/07158416.pdf [firstpage_image] =>[orig_patent_app_number] => 11081085 [rel_patent_id] =>[rel_patent_doc_number] =>)