Search

Scott A. Smith

Examiner (ID: 5262, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3204, 3727, 3721, 3616, 3205
Total Applications
3908
Issued Applications
3490
Pending Applications
118
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7621642 [patent_doc_number] => 06977859 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Semiconductor memory device and control method thereof' [patent_app_type] => utility [patent_app_number] => 11/076697 [patent_app_country] => US [patent_app_date] => 2005-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 14618 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977859.pdf [firstpage_image] =>[orig_patent_app_number] => 11076697 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/076697
Semiconductor memory device and control method thereof Mar 8, 2005 Issued
Array ( [id] => 6957047 [patent_doc_number] => 20050213417 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-29 [patent_title] => 'Circuit arrangement for latency regulation' [patent_app_type] => utility [patent_app_number] => 11/069789 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6215 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20050213417.pdf [firstpage_image] =>[orig_patent_app_number] => 11069789 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/069789
Circuit arrangement for latency regulation Feb 28, 2005 Issued
Array ( [id] => 7109797 [patent_doc_number] => 20050207251 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-09-22 [patent_title] => 'Integrated semiconductor memory with sense amplifier' [patent_app_type] => utility [patent_app_number] => 11/068491 [patent_app_country] => US [patent_app_date] => 2005-03-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9901 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20050207251.pdf [firstpage_image] =>[orig_patent_app_number] => 11068491 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/068491
Integrated semiconductor memory with sense amplifier Feb 28, 2005 Issued
Array ( [id] => 503442 [patent_doc_number] => 07209405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-24 [patent_title] => 'Memory device and method having multiple internal data buses and memory bank interleaving' [patent_app_type] => utility [patent_app_number] => 11/064543 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4148 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/209/07209405.pdf [firstpage_image] =>[orig_patent_app_number] => 11064543 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064543
Memory device and method having multiple internal data buses and memory bank interleaving Feb 22, 2005 Issued
Array ( [id] => 5765073 [patent_doc_number] => 20060018157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-26 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/058185 [patent_app_country] => US [patent_app_date] => 2005-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5260 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20060018157.pdf [firstpage_image] =>[orig_patent_app_number] => 11058185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/058185
Semiconductor memory device Feb 15, 2005 Issued
Array ( [id] => 545321 [patent_doc_number] => 07173868 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-02-06 [patent_title] => 'Sense amplifier of ferroelectric memory device' [patent_app_type] => utility [patent_app_number] => 11/057191 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4256 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/173/07173868.pdf [firstpage_image] =>[orig_patent_app_number] => 11057191 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057191
Sense amplifier of ferroelectric memory device Feb 14, 2005 Issued
Array ( [id] => 6965097 [patent_doc_number] => 20050231994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-20 [patent_title] => 'Ferroelectric nonvolatile code data output device' [patent_app_type] => utility [patent_app_number] => 11/057181 [patent_app_country] => US [patent_app_date] => 2005-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3232 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0231/20050231994.pdf [firstpage_image] =>[orig_patent_app_number] => 11057181 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057181
Ferroelectric nonvolatile code data output device Feb 14, 2005 Issued
Array ( [id] => 5676599 [patent_doc_number] => 20060181954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-17 [patent_title] => 'CIRCUIT AND METHOD FOR WRITING A BINARY VALUE TO A MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 11/057281 [patent_app_country] => US [patent_app_date] => 2005-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5297 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20060181954.pdf [firstpage_image] =>[orig_patent_app_number] => 11057281 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/057281
Circuit and method for writing a binary value to a memory cell Feb 10, 2005 Issued
Array ( [id] => 556824 [patent_doc_number] => 07170774 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-30 [patent_title] => 'Global bit line restore timing scheme and circuit' [patent_app_type] => utility [patent_app_number] => 11/054479 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1763 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/170/07170774.pdf [firstpage_image] =>[orig_patent_app_number] => 11054479 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054479
Global bit line restore timing scheme and circuit Feb 8, 2005 Issued
Array ( [id] => 5671407 [patent_doc_number] => 20060176761 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-10 [patent_title] => 'Clock generating circuit with multiple modes of operation' [patent_app_type] => utility [patent_app_number] => 11/054885 [patent_app_country] => US [patent_app_date] => 2005-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6354 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0176/20060176761.pdf [firstpage_image] =>[orig_patent_app_number] => 11054885 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054885
Clock generating circuit with multiple modes of operation Feb 8, 2005 Issued
Array ( [id] => 7073666 [patent_doc_number] => 20050146933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-07 [patent_title] => 'Method of reducing disturbs in non-volatile memory' [patent_app_type] => utility [patent_app_number] => 11/054084 [patent_app_country] => US [patent_app_date] => 2005-02-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8075 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20050146933.pdf [firstpage_image] =>[orig_patent_app_number] => 11054084 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/054084
Method of reducing disturbs in non-volatile memory Feb 7, 2005 Issued
Array ( [id] => 7096326 [patent_doc_number] => 20050128784 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Ferroelectric memory and data reading method for same' [patent_app_type] => utility [patent_app_number] => 11/050781 [patent_app_country] => US [patent_app_date] => 2005-02-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7643 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128784.pdf [firstpage_image] =>[orig_patent_app_number] => 11050781 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/050781
Ferroelectric memory and data reading method for same Feb 6, 2005 Issued
Array ( [id] => 7621638 [patent_doc_number] => 06977863 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-12-20 [patent_title] => 'Device and method for decoding an address word into word-line signals' [patent_app_type] => utility [patent_app_number] => 11/051594 [patent_app_country] => US [patent_app_date] => 2005-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3553 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 46 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/977/06977863.pdf [firstpage_image] =>[orig_patent_app_number] => 11051594 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/051594
Device and method for decoding an address word into word-line signals Feb 3, 2005 Issued
Array ( [id] => 7096351 [patent_doc_number] => 20050128809 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-16 [patent_title] => 'Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays' [patent_app_type] => utility [patent_app_number] => 11/046987 [patent_app_country] => US [patent_app_date] => 2005-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7471 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0128/20050128809.pdf [firstpage_image] =>[orig_patent_app_number] => 11046987 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/046987
Non-volatile semiconductor memory device in which one page is set for a plurality of memory cell arrays Jan 30, 2005 Issued
Array ( [id] => 7172508 [patent_doc_number] => 20050122804 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 11/041287 [patent_app_country] => US [patent_app_date] => 2005-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11986 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20050122804.pdf [firstpage_image] =>[orig_patent_app_number] => 11041287 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/041287
Shift redundancy circuit, method for controlling shift redundancy circuit, and semiconductor memory device Jan 24, 2005 Issued
Array ( [id] => 736688 [patent_doc_number] => 07038933 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Low voltage detector and method for detecting low voltage of FeRAM, and system using the same' [patent_app_type] => utility [patent_app_number] => 11/033762 [patent_app_country] => US [patent_app_date] => 2005-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7170 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/038/07038933.pdf [firstpage_image] =>[orig_patent_app_number] => 11033762 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/033762
Low voltage detector and method for detecting low voltage of FeRAM, and system using the same Jan 12, 2005 Issued
Array ( [id] => 5819223 [patent_doc_number] => 20060023536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-02-02 [patent_title] => 'Main amplifier and semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/032381 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3957 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20060023536.pdf [firstpage_image] =>[orig_patent_app_number] => 11032381 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032381
Main amplifier and semiconductor device Jan 9, 2005 Issued
Array ( [id] => 665619 [patent_doc_number] => 07102953 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-05 [patent_title] => 'Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell' [patent_app_type] => utility [patent_app_number] => 11/030185 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 24 [patent_no_of_words] => 13257 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/102/07102953.pdf [firstpage_image] =>[orig_patent_app_number] => 11030185 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/030185
Semiconductor memory device capable of operating at high speed and with low power consumption while ensuring reliability of memory cell Jan 6, 2005 Issued
Array ( [id] => 617848 [patent_doc_number] => 07145801 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-12-05 [patent_title] => 'External storage device' [patent_app_type] => utility [patent_app_number] => 11/031985 [patent_app_country] => US [patent_app_date] => 2005-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 22 [patent_no_of_words] => 11120 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/145/07145801.pdf [firstpage_image] =>[orig_patent_app_number] => 11031985 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/031985
External storage device Jan 6, 2005 Issued
Array ( [id] => 441297 [patent_doc_number] => 07259982 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-08-21 [patent_title] => 'Reading phase change memories to reduce read disturbs' [patent_app_type] => utility [patent_app_number] => 11/029981 [patent_app_country] => US [patent_app_date] => 2005-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5581 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/259/07259982.pdf [firstpage_image] =>[orig_patent_app_number] => 11029981 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/029981
Reading phase change memories to reduce read disturbs Jan 4, 2005 Issued
Menu