Search

Scott A. Smith

Examiner (ID: 5262, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3204, 3727, 3721, 3616, 3205
Total Applications
3908
Issued Applications
3490
Pending Applications
118
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7614399 [patent_doc_number] => 06898131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-24 [patent_title] => 'Voltage and temperature compensated pulse generator' [patent_app_type] => utility [patent_app_number] => 10/932858 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6986 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/898/06898131.pdf [firstpage_image] =>[orig_patent_app_number] => 10932858 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932858
Voltage and temperature compensated pulse generator Sep 1, 2004 Issued
Array ( [id] => 7150673 [patent_doc_number] => 20050024937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'High speed low voltage driver' [patent_app_type] => utility [patent_app_number] => 10/932413 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4039 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024937.pdf [firstpage_image] =>[orig_patent_app_number] => 10932413 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/932413
High speed low voltage driver Sep 1, 2004 Issued
Array ( [id] => 791366 [patent_doc_number] => 06985392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Byte aligned redundancy for memory array' [patent_app_type] => utility [patent_app_number] => 10/931698 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4155 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985392.pdf [firstpage_image] =>[orig_patent_app_number] => 10931698 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/931698
Byte aligned redundancy for memory array Aug 31, 2004 Issued
Array ( [id] => 674485 [patent_doc_number] => 07092313 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-15 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/929583 [patent_app_country] => US [patent_app_date] => 2004-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3375 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/092/07092313.pdf [firstpage_image] =>[orig_patent_app_number] => 10929583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929583
Semiconductor integrated circuit Aug 30, 2004 Issued
Array ( [id] => 6982131 [patent_doc_number] => 20050152200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Semiconductor memory having variable memory size and method for refreshing the same' [patent_app_type] => utility [patent_app_number] => 10/928191 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7528 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0152/20050152200.pdf [firstpage_image] =>[orig_patent_app_number] => 10928191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928191
Semiconductor memory having variable memory size and method for refreshing the same Aug 29, 2004 Issued
Array ( [id] => 7196166 [patent_doc_number] => 20050041476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/929014 [patent_app_country] => US [patent_app_date] => 2004-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 56 [patent_figures_cnt] => 56 [patent_no_of_words] => 33205 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0041/20050041476.pdf [firstpage_image] =>[orig_patent_app_number] => 10929014 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/929014
Nonvolatile semiconductor memory Aug 29, 2004 Issued
10/927883 Temperature-dependent DRAM self-refresh circuit Aug 26, 2004 Abandoned
Array ( [id] => 7038129 [patent_doc_number] => 20050157563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-21 [patent_title] => 'Memory Device and mobile communication device using a specific access procedure' [patent_app_type] => utility [patent_app_number] => 10/927391 [patent_app_country] => US [patent_app_date] => 2004-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2045 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20050157563.pdf [firstpage_image] =>[orig_patent_app_number] => 10927391 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/927391
Memory Device and mobile communication device using a specific access procedure Aug 25, 2004 Abandoned
Array ( [id] => 1019864 [patent_doc_number] => 06891770 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Fully hidden refresh dynamic random access memory' [patent_app_type] => utility [patent_app_number] => 10/920421 [patent_app_country] => US [patent_app_date] => 2004-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 31 [patent_no_of_words] => 20732 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/891/06891770.pdf [firstpage_image] =>[orig_patent_app_number] => 10920421 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/920421
Fully hidden refresh dynamic random access memory Aug 17, 2004 Issued
Array ( [id] => 997864 [patent_doc_number] => 06914838 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Dual loop sensing scheme for resistive memory elements' [patent_app_type] => utility [patent_app_number] => 10/918453 [patent_app_country] => US [patent_app_date] => 2004-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 5092 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914838.pdf [firstpage_image] =>[orig_patent_app_number] => 10918453 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/918453
Dual loop sensing scheme for resistive memory elements Aug 15, 2004 Issued
Array ( [id] => 7121331 [patent_doc_number] => 20050013160 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-20 [patent_title] => 'Semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/917321 [patent_app_country] => US [patent_app_date] => 2004-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 10649 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20050013160.pdf [firstpage_image] =>[orig_patent_app_number] => 10917321 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/917321
Semiconductor memory device Aug 12, 2004 Issued
Array ( [id] => 949481 [patent_doc_number] => 06963517 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Parallel asynchronous propagation pipeline structure to access multiple memory arrays' [patent_app_type] => utility [patent_app_number] => 10/916087 [patent_app_country] => US [patent_app_date] => 2004-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 4991 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963517.pdf [firstpage_image] =>[orig_patent_app_number] => 10916087 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/916087
Parallel asynchronous propagation pipeline structure to access multiple memory arrays Aug 9, 2004 Issued
Array ( [id] => 7087735 [patent_doc_number] => 20050007847 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Method and apparatus for saving current in a memory device' [patent_app_type] => utility [patent_app_number] => 10/915155 [patent_app_country] => US [patent_app_date] => 2004-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007847.pdf [firstpage_image] =>[orig_patent_app_number] => 10915155 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/915155
Method and apparatus for saving current in a memory device Aug 8, 2004 Issued
Array ( [id] => 7087725 [patent_doc_number] => 20050007837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-13 [patent_title] => 'Clock generator for pseudo dual port memory' [patent_app_type] => utility [patent_app_number] => 10/911457 [patent_app_country] => US [patent_app_date] => 2004-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3133 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0007/20050007837.pdf [firstpage_image] =>[orig_patent_app_number] => 10911457 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/911457
Clock generator for pseudo dual port memory Aug 3, 2004 Issued
Array ( [id] => 949475 [patent_doc_number] => 06963511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-08 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 10/900287 [patent_app_country] => US [patent_app_date] => 2004-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10560 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/963/06963511.pdf [firstpage_image] =>[orig_patent_app_number] => 10900287 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/900287
Semiconductor integrated circuit Jul 27, 2004 Issued
Array ( [id] => 7415483 [patent_doc_number] => 20040264258 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'ROM embedded DRAM with bias sensing' [patent_app_type] => new [patent_app_number] => 10/899894 [patent_app_country] => US [patent_app_date] => 2004-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4918 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0264/20040264258.pdf [firstpage_image] =>[orig_patent_app_number] => 10899894 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/899894
ROM embedded DRAM with bias sensing Jul 26, 2004 Issued
Array ( [id] => 942235 [patent_doc_number] => 06970384 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-11-29 [patent_title] => 'Programming method of flash memory device' [patent_app_type] => utility [patent_app_number] => 10/893585 [patent_app_country] => US [patent_app_date] => 2004-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2899 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/970/06970384.pdf [firstpage_image] =>[orig_patent_app_number] => 10893585 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/893585
Programming method of flash memory device Jul 15, 2004 Issued
Array ( [id] => 936182 [patent_doc_number] => 06975532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-13 [patent_title] => 'Quasi-static random access memory' [patent_app_type] => utility [patent_app_number] => 10/887983 [patent_app_country] => US [patent_app_date] => 2004-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 4285 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/975/06975532.pdf [firstpage_image] =>[orig_patent_app_number] => 10887983 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/887983
Quasi-static random access memory Jul 7, 2004 Issued
Array ( [id] => 788763 [patent_doc_number] => 06987697 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-17 [patent_title] => 'Memory device' [patent_app_type] => utility [patent_app_number] => 10/885083 [patent_app_country] => US [patent_app_date] => 2004-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 17006 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/987/06987697.pdf [firstpage_image] =>[orig_patent_app_number] => 10885083 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/885083
Memory device Jul 6, 2004 Issued
Array ( [id] => 7024080 [patent_doc_number] => 20050018474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-27 [patent_title] => 'SRAM cell structure and circuits' [patent_app_type] => utility [patent_app_number] => 10/883581 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7052 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0018/20050018474.pdf [firstpage_image] =>[orig_patent_app_number] => 10883581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/883581
SRAM cell structure and circuits Jun 29, 2004 Issued
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