Search

Scott A. Smith

Examiner (ID: 5262, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3204, 3727, 3721, 3616, 3205
Total Applications
3908
Issued Applications
3490
Pending Applications
118
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 628373 [patent_doc_number] => 07136298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-11-14 [patent_title] => 'Magnetic random access memory array with global write lines' [patent_app_type] => utility [patent_app_number] => 10/880981 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 5013 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/136/07136298.pdf [firstpage_image] =>[orig_patent_app_number] => 10880981 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/880981
Magnetic random access memory array with global write lines Jun 29, 2004 Issued
Array ( [id] => 5893641 [patent_doc_number] => 20060002179 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'METHOD AND STRUCTURE FOR SELECTING ANISOTROPY AXIS ANGLE OF MRAM DEVICE FOR REDUCED POWER CONSUMPTION' [patent_app_type] => utility [patent_app_number] => 10/710281 [patent_app_country] => US [patent_app_date] => 2004-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4642 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20060002179.pdf [firstpage_image] =>[orig_patent_app_number] => 10710281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/710281
Method and structure for selecting anisotropy axis angle of MRAM device for reduced power consumption Jun 29, 2004 Issued
Array ( [id] => 1051730 [patent_doc_number] => 06862250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Circuit and method for generating output control signal in synchronous semiconductor memory device' [patent_app_type] => utility [patent_app_number] => 10/877986 [patent_app_country] => US [patent_app_date] => 2004-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7724 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862250.pdf [firstpage_image] =>[orig_patent_app_number] => 10877986 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/877986
Circuit and method for generating output control signal in synchronous semiconductor memory device Jun 28, 2004 Issued
Array ( [id] => 1051709 [patent_doc_number] => 06862240 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-01 [patent_title] => 'Variable refresh control for a memory' [patent_app_type] => utility [patent_app_number] => 10/878956 [patent_app_country] => US [patent_app_date] => 2004-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3749 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/862/06862240.pdf [firstpage_image] =>[orig_patent_app_number] => 10878956 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/878956
Variable refresh control for a memory Jun 27, 2004 Issued
Array ( [id] => 7413910 [patent_doc_number] => 20040228176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-18 [patent_title] => 'Semiconductor memory device having a hierarchical I/O structure' [patent_app_type] => new [patent_app_number] => 10/875209 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 19338 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 3 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0228/20040228176.pdf [firstpage_image] =>[orig_patent_app_number] => 10875209 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875209
Semiconductor memory device having a hierarchical I/O structure Jun 24, 2004 Issued
Array ( [id] => 793877 [patent_doc_number] => 06982924 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-03 [patent_title] => 'Data output control circuit' [patent_app_type] => utility [patent_app_number] => 10/875387 [patent_app_country] => US [patent_app_date] => 2004-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4828 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/982/06982924.pdf [firstpage_image] =>[orig_patent_app_number] => 10875387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875387
Data output control circuit Jun 24, 2004 Issued
Array ( [id] => 639779 [patent_doc_number] => 07126869 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-10-24 [patent_title] => 'Sense amplifier with dual cascode transistors and improved noise margin' [patent_app_type] => utility [patent_app_number] => 10/875889 [patent_app_country] => US [patent_app_date] => 2004-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 7144 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/126/07126869.pdf [firstpage_image] =>[orig_patent_app_number] => 10875889 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/875889
Sense amplifier with dual cascode transistors and improved noise margin Jun 23, 2004 Issued
Array ( [id] => 723435 [patent_doc_number] => 07050341 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-23 [patent_title] => 'Diagonal matrix delay' [patent_app_type] => utility [patent_app_number] => 10/873591 [patent_app_country] => US [patent_app_date] => 2004-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6050 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/050/07050341.pdf [firstpage_image] =>[orig_patent_app_number] => 10873591 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/873591
Diagonal matrix delay Jun 22, 2004 Issued
Array ( [id] => 7604349 [patent_doc_number] => 07116587 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-03 [patent_title] => 'Charge pump for programmable semiconductor memory' [patent_app_type] => utility [patent_app_number] => 10/869085 [patent_app_country] => US [patent_app_date] => 2004-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2133 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/116/07116587.pdf [firstpage_image] =>[orig_patent_app_number] => 10869085 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/869085
Charge pump for programmable semiconductor memory Jun 15, 2004 Issued
Array ( [id] => 7150701 [patent_doc_number] => 20050024952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-03 [patent_title] => 'Word-programmable flash memory' [patent_app_type] => utility [patent_app_number] => 10/867381 [patent_app_country] => US [patent_app_date] => 2004-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5067 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20050024952.pdf [firstpage_image] =>[orig_patent_app_number] => 10867381 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/867381
Word-programmable flash memory Jun 13, 2004 Issued
Array ( [id] => 1045377 [patent_doc_number] => 06868011 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-15 [patent_title] => 'Apparatus and method for interfacing between modem and memory in mobile station' [patent_app_type] => utility [patent_app_number] => 10/865645 [patent_app_country] => US [patent_app_date] => 2004-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6330 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/868/06868011.pdf [firstpage_image] =>[orig_patent_app_number] => 10865645 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/865645
Apparatus and method for interfacing between modem and memory in mobile station Jun 9, 2004 Issued
Array ( [id] => 6904486 [patent_doc_number] => 20050099881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-12 [patent_title] => 'Apparatus for interleave and method thereof' [patent_app_type] => utility [patent_app_number] => 10/861485 [patent_app_country] => US [patent_app_date] => 2004-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 14980 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20050099881.pdf [firstpage_image] =>[orig_patent_app_number] => 10861485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/861485
Apparatus for interleave and method thereof Jun 6, 2004 Issued
Array ( [id] => 614194 [patent_doc_number] => 07149142 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-12-12 [patent_title] => 'Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry' [patent_app_type] => utility [patent_app_number] => 10/856191 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5595 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/149/07149142.pdf [firstpage_image] =>[orig_patent_app_number] => 10856191 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856191
Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry May 27, 2004 Issued
Array ( [id] => 682528 [patent_doc_number] => 07085182 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Fuse blowing interface for a memory chip' [patent_app_type] => utility [patent_app_number] => 10/856685 [patent_app_country] => US [patent_app_date] => 2004-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 18 [patent_no_of_words] => 9207 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085182.pdf [firstpage_image] =>[orig_patent_app_number] => 10856685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856685
Fuse blowing interface for a memory chip May 27, 2004 Issued
Array ( [id] => 939198 [patent_doc_number] => 06972987 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-12-06 [patent_title] => 'Techniques for reducing power consumption in memory cells' [patent_app_type] => utility [patent_app_number] => 10/856187 [patent_app_country] => US [patent_app_date] => 2004-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3500 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/972/06972987.pdf [firstpage_image] =>[orig_patent_app_number] => 10856187 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/856187
Techniques for reducing power consumption in memory cells May 26, 2004 Issued
Array ( [id] => 697620 [patent_doc_number] => 07072211 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-07-04 [patent_title] => 'Systems and methods for write protection of non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 10/849485 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6401 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/072/07072211.pdf [firstpage_image] =>[orig_patent_app_number] => 10849485 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849485
Systems and methods for write protection of non-volatile memory devices May 18, 2004 Issued
Array ( [id] => 7059884 [patent_doc_number] => 20050002244 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor storage device, redundancy circuit thereof, and portable electronic device' [patent_app_type] => utility [patent_app_number] => 10/848481 [patent_app_country] => US [patent_app_date] => 2004-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 20629 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002244.pdf [firstpage_image] =>[orig_patent_app_number] => 10848481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/848481
Semiconductor storage device, redundancy circuit thereof, and portable electronic device May 18, 2004 Issued
Array ( [id] => 682501 [patent_doc_number] => 07085166 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'Semiconductor memory device and programming method thereof' [patent_app_type] => utility [patent_app_number] => 10/847587 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 20491 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/085/07085166.pdf [firstpage_image] =>[orig_patent_app_number] => 10847587 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/847587
Semiconductor memory device and programming method thereof May 17, 2004 Issued
Array ( [id] => 7059880 [patent_doc_number] => 20050002240 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-01-06 [patent_title] => 'Semiconductor memory device and portable electronic apparatus' [patent_app_type] => utility [patent_app_number] => 10/849481 [patent_app_country] => US [patent_app_date] => 2004-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 25699 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20050002240.pdf [firstpage_image] =>[orig_patent_app_number] => 10849481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/849481
Semiconductor memory device and portable electronic apparatus May 17, 2004 Issued
Array ( [id] => 7032272 [patent_doc_number] => 20050030781 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method and arrangement for testing output circuits of high speed semiconductor memory devices' [patent_app_type] => utility [patent_app_number] => 10/843383 [patent_app_country] => US [patent_app_date] => 2004-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4275 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20050030781.pdf [firstpage_image] =>[orig_patent_app_number] => 10843383 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/843383
Method and arrangement for testing output circuits of high speed semiconductor memory devices May 11, 2004 Issued
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