Search

Scott A. Smith

Examiner (ID: 231, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3727, 3204, 3205, 3616, 3721
Total Applications
3908
Issued Applications
3490
Pending Applications
120
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18820835 [patent_doc_number] => 20230395176 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-07 [patent_title] => MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/205083 [patent_app_country] => US [patent_app_date] => 2023-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7839 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18205083 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/205083
MEMORY SUB-SYSTEM THRESHOLD VOLTAGE MODIFICATION OPERATIONS Jun 1, 2023 Pending
Array ( [id] => 20469263 [patent_doc_number] => 12525305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-01-13 [patent_title] => Memory device and enhance programming method thereof [patent_app_type] => utility [patent_app_number] => 18/319501 [patent_app_country] => US [patent_app_date] => 2023-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18319501 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/319501
Memory device and enhance programming method thereof May 17, 2023 Issued
Array ( [id] => 18630211 [patent_doc_number] => 20230289103 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-14 [patent_title] => MANAGEMENT OF NON-VOLATILE MEMORY ARRAYS [patent_app_type] => utility [patent_app_number] => 18/315932 [patent_app_country] => US [patent_app_date] => 2023-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10295 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18315932 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/315932
MANAGEMENT OF NON-VOLATILE MEMORY ARRAYS May 10, 2023 Abandoned
Array ( [id] => 18569401 [patent_doc_number] => 20230259738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-17 [patent_title] => MEMORY DEVICE OF NON-VOLATILE MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/141090 [patent_app_country] => US [patent_app_date] => 2023-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8216 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18141090 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/141090
Memory device of non-volatile memory cells Apr 27, 2023 Issued
Array ( [id] => 19670663 [patent_doc_number] => 12183430 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-31 [patent_title] => Communicating print component [patent_app_type] => utility [patent_app_number] => 18/135697 [patent_app_country] => US [patent_app_date] => 2023-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 12995 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18135697 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/135697
Communicating print component Apr 16, 2023 Issued
Array ( [id] => 18555002 [patent_doc_number] => 20230253018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-10 [patent_title] => METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING A SELECTIVE LEVEL CHANGE, A METHOD OF TRANSMITTING DATA USING THE SAME, AND A TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME [patent_app_type] => utility [patent_app_number] => 18/134618 [patent_app_country] => US [patent_app_date] => 2023-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15229 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 315 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18134618 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/134618
Method of generating a multi-level signal using a selective level change, a method of transmitting data using the same, and a transmitter and memory system performing the same Apr 13, 2023 Issued
Array ( [id] => 20117453 [patent_doc_number] => 12367159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Low latency memory access [patent_app_type] => utility [patent_app_number] => 18/133700 [patent_app_country] => US [patent_app_date] => 2023-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 5409 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18133700 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/133700
Low latency memory access Apr 11, 2023 Issued
Array ( [id] => 20416631 [patent_doc_number] => 12499920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-12-16 [patent_title] => Activation functions for artificial intelligence operations [patent_app_type] => utility [patent_app_number] => 18/131600 [patent_app_country] => US [patent_app_date] => 2023-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11950 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18131600 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/131600
Activation functions for artificial intelligence operations Apr 5, 2023 Issued
Array ( [id] => 19964648 [patent_doc_number] => 12334163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-06-17 [patent_title] => Single-level cell program-verify, latch-limited data recovery [patent_app_type] => utility [patent_app_number] => 18/128463 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8370 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18128463 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/128463
Single-level cell program-verify, latch-limited data recovery Mar 29, 2023 Issued
Array ( [id] => 19160839 [patent_doc_number] => 20240153546 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-09 [patent_title] => MEMORY DEVICE FOR PERFORMING READ PROTECTION OPERATION OF LIMITING READ OPERATION AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 18/192938 [patent_app_country] => US [patent_app_date] => 2023-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7134 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18192938 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/192938
Memory device for performing read protection operation of limiting read operation and method of operating the same Mar 29, 2023 Issued
Array ( [id] => 18659710 [patent_doc_number] => 20230305717 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => CORRECTIVE READS IMPLEMENTING INCREMENTAL READS WITH RESPECT TO ADJACENT WORDLINES [patent_app_type] => utility [patent_app_number] => 18/125279 [patent_app_country] => US [patent_app_date] => 2023-03-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10821 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18125279 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/125279
Corrective reads implementing incremental reads with respect to adjacent wordlines Mar 22, 2023 Issued
Array ( [id] => 19886699 [patent_doc_number] => 12272424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Reducing spurious write operations in a memory device [patent_app_type] => utility [patent_app_number] => 18/124489 [patent_app_country] => US [patent_app_date] => 2023-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4280 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18124489 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/124489
Reducing spurious write operations in a memory device Mar 20, 2023 Issued
Array ( [id] => 18958788 [patent_doc_number] => 20240047115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-08 [patent_title] => SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS [patent_app_type] => utility [patent_app_number] => 18/123418 [patent_app_country] => US [patent_app_date] => 2023-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2762 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -1 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18123418 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/123418
SWITCHING OF PERPENDICULARLY MAGNETIZED NANOMAGNETS WITH SPIN-ORBIT TORQUES IN THE ABSENCE OF EXTERNAL MAGNETIC FIELDS Mar 19, 2023 Abandoned
Array ( [id] => 19054454 [patent_doc_number] => 20240096423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/177685 [patent_app_country] => US [patent_app_date] => 2023-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20628 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18177685 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/177685
MEMORY SYSTEM Mar 1, 2023 Pending
Array ( [id] => 19858051 [patent_doc_number] => 12260901 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Signal input buffer for effectively calibrating offset [patent_app_type] => utility [patent_app_number] => 18/099744 [patent_app_country] => US [patent_app_date] => 2023-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 12175 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 551 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18099744 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/099744
Signal input buffer for effectively calibrating offset Jan 19, 2023 Issued
Array ( [id] => 18333153 [patent_doc_number] => 20230125101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => NONVOLATILE MEMORY DEVICE AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/088046 [patent_app_country] => US [patent_app_date] => 2022-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15704 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18088046 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/088046
Nonvolatile memory device and operation method of detecting defective memory cells Dec 22, 2022 Issued
Array ( [id] => 18455883 [patent_doc_number] => 20230197164 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-22 [patent_title] => BIAS VOLTAGE SCHEMES DURING PRE-PROGRAMMING AND PROGRAMMING PHASES [patent_app_type] => utility [patent_app_number] => 18/076537 [patent_app_country] => US [patent_app_date] => 2022-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11715 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18076537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/076537
Bias voltage schemes during pre-programming and programming phases Dec 6, 2022 Issued
Array ( [id] => 18408681 [patent_doc_number] => 20230170034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => MEMORY DEVICE AND PROGRAM OPERATION THEREOF [patent_app_type] => utility [patent_app_number] => 18/071026 [patent_app_country] => US [patent_app_date] => 2022-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5874 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18071026 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/071026
Memory device and program operation thereof to reduce capacitive coupling Nov 28, 2022 Issued
Array ( [id] => 20581196 [patent_doc_number] => 12573450 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => SRAM column sleep circuits for leakage savings with rapid wake [patent_app_type] => utility [patent_app_number] => 18/059360 [patent_app_country] => US [patent_app_date] => 2022-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2329 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18059360 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/059360
SRAM column sleep circuits for leakage savings with rapid wake Nov 27, 2022 Issued
Array ( [id] => 19507630 [patent_doc_number] => 12119059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Write method for differential resistive memories [patent_app_type] => utility [patent_app_number] => 17/990723 [patent_app_country] => US [patent_app_date] => 2022-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 7270 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 307 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17990723 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/990723
Write method for differential resistive memories Nov 19, 2022 Issued
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