Search

Scott A. Smith

Examiner (ID: 5262, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3204, 3727, 3721, 3616, 3205
Total Applications
3908
Issued Applications
3490
Pending Applications
118
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 969850 [patent_doc_number] => 06940749 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'MRAM array with segmented word and bit lines' [patent_app_type] => utility [patent_app_number] => 10/669481 [patent_app_country] => US [patent_app_date] => 2003-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 9516 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/940/06940749.pdf [firstpage_image] =>[orig_patent_app_number] => 10669481 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/669481
MRAM array with segmented word and bit lines Sep 22, 2003 Issued
Array ( [id] => 7146288 [patent_doc_number] => 20040170041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-02 [patent_title] => 'CAM cells for high speed and lower power content addressable memory (CAM) and ternary content addressable memory (TCAM)' [patent_app_type] => new [patent_app_number] => 10/667679 [patent_app_country] => US [patent_app_date] => 2003-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13087 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0170/20040170041.pdf [firstpage_image] =>[orig_patent_app_number] => 10667679 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/667679
CAM cells for high speed and lower power content addressable memory (CAM) and ternary content addressable memory (TCAM) Sep 21, 2003 Abandoned
Array ( [id] => 1029528 [patent_doc_number] => 06882574 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-19 [patent_title] => 'Single poly UV-erasable programmable read only memory' [patent_app_type] => utility [patent_app_number] => 10/605235 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2879 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/882/06882574.pdf [firstpage_image] =>[orig_patent_app_number] => 10605235 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/605235
Single poly UV-erasable programmable read only memory Sep 16, 2003 Issued
Array ( [id] => 786482 [patent_doc_number] => 06990024 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-24 [patent_title] => 'Thin film magnetic memory device having data read current tuning function' [patent_app_type] => utility [patent_app_number] => 10/663674 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 25 [patent_no_of_words] => 16626 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/990/06990024.pdf [firstpage_image] =>[orig_patent_app_number] => 10663674 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/663674
Thin film magnetic memory device having data read current tuning function Sep 16, 2003 Issued
Array ( [id] => 7009495 [patent_doc_number] => 20050063211 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Random access memory having an adaptable latency' [patent_app_type] => utility [patent_app_number] => 10/664789 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 11190 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0063/20050063211.pdf [firstpage_image] =>[orig_patent_app_number] => 10664789 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/664789
Random access memory having an adaptable latency Sep 16, 2003 Issued
Array ( [id] => 7126224 [patent_doc_number] => 20050057968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-17 [patent_title] => 'Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance' [patent_app_type] => utility [patent_app_number] => 10/665685 [patent_app_country] => US [patent_app_date] => 2003-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6775 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20050057968.pdf [firstpage_image] =>[orig_patent_app_number] => 10665685 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/665685
Methods for identifying non-volatile memory elements with poor subthreshold slope or weak transconductance Sep 16, 2003 Issued
Array ( [id] => 1163895 [patent_doc_number] => 06765844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-07-20 [patent_title] => 'Semiconductor memory device having a hierarchical I/O structure' [patent_app_type] => B2 [patent_app_number] => 10/658396 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 17 [patent_no_of_words] => 19216 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/765/06765844.pdf [firstpage_image] =>[orig_patent_app_number] => 10658396 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658396
Semiconductor memory device having a hierarchical I/O structure Sep 9, 2003 Issued
Array ( [id] => 7162981 [patent_doc_number] => 20040076061 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'On-system programmable and off-system programmable chip' [patent_app_type] => new [patent_app_number] => 10/658289 [patent_app_country] => US [patent_app_date] => 2003-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3463 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20040076061.pdf [firstpage_image] =>[orig_patent_app_number] => 10658289 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658289
On-system programmable and off-system programmable chip Sep 9, 2003 Issued
Array ( [id] => 1000763 [patent_doc_number] => 06912163 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-28 [patent_title] => 'Memory device having high work function gate and method of erasing same' [patent_app_type] => utility [patent_app_number] => 10/658506 [patent_app_country] => US [patent_app_date] => 2003-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6528 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/912/06912163.pdf [firstpage_image] =>[orig_patent_app_number] => 10658506 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/658506
Memory device having high work function gate and method of erasing same Sep 8, 2003 Issued
Array ( [id] => 7204265 [patent_doc_number] => 20050052893 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Data storage device and method of forming the same' [patent_app_type] => utility [patent_app_number] => 10/657385 [patent_app_country] => US [patent_app_date] => 2003-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4191 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0052/20050052893.pdf [firstpage_image] =>[orig_patent_app_number] => 10657385 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/657385
Data storage device and method of forming the same Sep 7, 2003 Issued
Array ( [id] => 791368 [patent_doc_number] => 06985394 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-10 [patent_title] => 'Integrated circuit devices including input/output line pairs and precharge circuits and related memory devices' [patent_app_type] => utility [patent_app_number] => 10/651181 [patent_app_country] => US [patent_app_date] => 2003-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 4931 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/985/06985394.pdf [firstpage_image] =>[orig_patent_app_number] => 10651181 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/651181
Integrated circuit devices including input/output line pairs and precharge circuits and related memory devices Aug 27, 2003 Issued
Array ( [id] => 7386199 [patent_doc_number] => 20040037130 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Voltage and temperature compensated pulse generator' [patent_app_type] => new [patent_app_number] => 10/642958 [patent_app_country] => US [patent_app_date] => 2003-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6998 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20040037130.pdf [firstpage_image] =>[orig_patent_app_number] => 10642958 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642958
Voltage and temperature compensated pulse generator Aug 17, 2003 Issued
Array ( [id] => 983518 [patent_doc_number] => 06927993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-08-09 [patent_title] => 'Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells' [patent_app_type] => utility [patent_app_number] => 10/642079 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 28 [patent_no_of_words] => 7214 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 390 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/927/06927993.pdf [firstpage_image] =>[orig_patent_app_number] => 10642079 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/642079
Multi-bit ROM cell, for storing on of N>4 possible states and having bi-directional read, an array of such cells Aug 13, 2003 Issued
Array ( [id] => 1130884 [patent_doc_number] => 06791855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-14 [patent_title] => 'Redundant array architecture for word replacement in CAM' [patent_app_type] => B2 [patent_app_number] => 10/641753 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1995 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/791/06791855.pdf [firstpage_image] =>[orig_patent_app_number] => 10641753 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641753
Redundant array architecture for word replacement in CAM Aug 13, 2003 Issued
Array ( [id] => 7451655 [patent_doc_number] => 20040196724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-10-07 [patent_title] => 'Leakage current reduction for CMOS memory circuits' [patent_app_type] => new [patent_app_number] => 10/641883 [patent_app_country] => US [patent_app_date] => 2003-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7255 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0196/20040196724.pdf [firstpage_image] =>[orig_patent_app_number] => 10641883 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641883
Leakage current reduction for CMOS memory circuits Aug 13, 2003 Issued
Array ( [id] => 1118214 [patent_doc_number] => 06801458 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-10-05 [patent_title] => 'Nonvolatile semiconductor memory' [patent_app_type] => B2 [patent_app_number] => 10/638406 [patent_app_country] => US [patent_app_date] => 2003-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 55 [patent_figures_cnt] => 74 [patent_no_of_words] => 33117 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/801/06801458.pdf [firstpage_image] =>[orig_patent_app_number] => 10638406 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/638406
Nonvolatile semiconductor memory Aug 11, 2003 Issued
Array ( [id] => 7374744 [patent_doc_number] => 20040027885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-12 [patent_title] => 'Device and method for decoding an address word into word-line signals' [patent_app_type] => new [patent_app_number] => 10/636387 [patent_app_country] => US [patent_app_date] => 2003-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3538 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0027/20040027885.pdf [firstpage_image] =>[orig_patent_app_number] => 10636387 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/636387
Device and method for decoding an address word into word-line signals Aug 6, 2003 Issued
Array ( [id] => 1091297 [patent_doc_number] => 06829196 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-12-07 [patent_title] => 'Method and apparatus for prevention of read corruption in rotated-read register files and content addressable memory arrays' [patent_app_type] => B1 [patent_app_number] => 10/631379 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5794 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/829/06829196.pdf [firstpage_image] =>[orig_patent_app_number] => 10631379 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631379
Method and apparatus for prevention of read corruption in rotated-read register files and content addressable memory arrays Jul 29, 2003 Issued
Array ( [id] => 1095643 [patent_doc_number] => 06826114 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-30 [patent_title] => 'Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset method' [patent_app_type] => B2 [patent_app_number] => 10/624783 [patent_app_country] => US [patent_app_date] => 2003-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3265 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/826/06826114.pdf [firstpage_image] =>[orig_patent_app_number] => 10624783 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/624783
Data path reset circuit using clock enable signal, reset method, and semiconductor memory device including the data path reset circuit and adopting the reset method Jul 21, 2003 Issued
Array ( [id] => 1042165 [patent_doc_number] => 06870787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'Configuration and method for checking an address generator' [patent_app_type] => utility [patent_app_number] => 10/620587 [patent_app_country] => US [patent_app_date] => 2003-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2725 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/870/06870787.pdf [firstpage_image] =>[orig_patent_app_number] => 10620587 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/620587
Configuration and method for checking an address generator Jul 15, 2003 Issued
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