Search

Scott A. Smith

Examiner (ID: 231, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3727, 3204, 3205, 3616, 3721
Total Applications
3908
Issued Applications
3490
Pending Applications
120
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19733582 [patent_doc_number] => 12211582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-28 [patent_title] => Signed and binary weighted computation for an in-memory computation system [patent_app_type] => utility [patent_app_number] => 17/718755 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 27 [patent_no_of_words] => 15893 [patent_no_of_claims] => 52 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718755 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718755
Signed and binary weighted computation for an in-memory computation system Apr 11, 2022 Issued
Array ( [id] => 18623540 [patent_doc_number] => 11756593 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Memory control circuit, information processing system, and memory control method [patent_app_type] => utility [patent_app_number] => 17/718796 [patent_app_country] => US [patent_app_date] => 2022-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8326 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718796 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718796
Memory control circuit, information processing system, and memory control method Apr 11, 2022 Issued
Array ( [id] => 18229672 [patent_doc_number] => 20230068666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => METHODS FOR OPTIMIZING SEMICONDUCTOR DEVICE PLACEMENT ON A SUBSTRATE FOR IMPROVED PERFORMANCE, AND ASSOCIATED SYSTEMS AND METHODS [patent_app_type] => utility [patent_app_number] => 17/718200 [patent_app_country] => US [patent_app_date] => 2022-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9515 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17718200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/718200
Methods for optimizing semiconductor device placement on a substrate for improved performance, and associated systems and methods Apr 10, 2022 Issued
Array ( [id] => 17752495 [patent_doc_number] => 20220230700 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => INTELLIGENT MEMORY DEVICE TEST RACK [patent_app_type] => utility [patent_app_number] => 17/716972 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11283 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716972 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716972
Intelligent memory device test rack Apr 7, 2022 Issued
Array ( [id] => 17886142 [patent_doc_number] => 20220301619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => READING A MULTI-LEVEL MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/716740 [patent_app_country] => US [patent_app_date] => 2022-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19357 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17716740 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/716740
Reading a multi-level memory cell Apr 7, 2022 Issued
Array ( [id] => 18319447 [patent_doc_number] => 20230117575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/710621 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15004 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17710621 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/710621
Semiconductor memory device and method of perfomring a multi-level sensing operation Mar 30, 2022 Issued
Array ( [id] => 19213464 [patent_doc_number] => 12002536 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Sensing module, memory device, and sensing method applied to identify un-programmed/programmed state of non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 17/705469 [patent_app_country] => US [patent_app_date] => 2022-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 22 [patent_no_of_words] => 8873 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17705469 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/705469
Sensing module, memory device, and sensing method applied to identify un-programmed/programmed state of non-volatile memory cell Mar 27, 2022 Issued
Array ( [id] => 18623594 [patent_doc_number] => 11756648 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-09-12 [patent_title] => Semiconductor device having redundancy word lines [patent_app_type] => utility [patent_app_number] => 17/692049 [patent_app_country] => US [patent_app_date] => 2022-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3476 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17692049 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/692049
Semiconductor device having redundancy word lines Mar 9, 2022 Issued
Array ( [id] => 19376474 [patent_doc_number] => 12068052 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-08-20 [patent_title] => Preserving blocks experiencing program failure in memory devices [patent_app_type] => utility [patent_app_number] => 17/682064 [patent_app_country] => US [patent_app_date] => 2022-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 11132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17682064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/682064
Preserving blocks experiencing program failure in memory devices Feb 27, 2022 Issued
Array ( [id] => 18585742 [patent_doc_number] => 20230268006 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-08-24 [patent_title] => GENERATING PATTERNS FOR MEMORY THRESHOLD VOLTAGE DIFFERENCE [patent_app_type] => utility [patent_app_number] => 17/680042 [patent_app_country] => US [patent_app_date] => 2022-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5938 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17680042 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/680042
Generating patterns for memory threshold voltage difference Feb 23, 2022 Issued
Array ( [id] => 18874466 [patent_doc_number] => 11862287 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-02 [patent_title] => Managing page buffer circuits in memory devices [patent_app_type] => utility [patent_app_number] => 17/674132 [patent_app_country] => US [patent_app_date] => 2022-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 11 [patent_no_of_words] => 13046 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17674132 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/674132
Managing page buffer circuits in memory devices Feb 16, 2022 Issued
Array ( [id] => 18196144 [patent_doc_number] => 20230049663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => ADDRESS CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 17/670892 [patent_app_country] => US [patent_app_date] => 2022-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5358 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17670892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/670892
ADDRESS CONTROL CIRCUIT AND SEMICONDUCTOR APPARATUS INCLUDING THE SAME Feb 13, 2022 Abandoned
Array ( [id] => 19016095 [patent_doc_number] => 11923035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Pseudo dual port memory devices [patent_app_type] => utility [patent_app_number] => 17/668760 [patent_app_country] => US [patent_app_date] => 2022-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12868 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17668760 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/668760
Pseudo dual port memory devices Feb 9, 2022 Issued
Array ( [id] => 18431444 [patent_doc_number] => 11676671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-06-13 [patent_title] => Amplification-based read disturb information determination system [patent_app_type] => utility [patent_app_number] => 17/581882 [patent_app_country] => US [patent_app_date] => 2022-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 23360 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581882 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581882
Amplification-based read disturb information determination system Jan 21, 2022 Issued
Array ( [id] => 18080734 [patent_doc_number] => 20220406346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => SEMICONDUCTOR CHIP AND VEHICLE COMPRISING THE SAME [patent_app_type] => utility [patent_app_number] => 17/580702 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12530 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580702 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580702
Semiconductor chip and vehicle comprising the same Jan 20, 2022 Issued
Array ( [id] => 19016102 [patent_doc_number] => 11923042 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-05 [patent_title] => Apparatus, memory device, and method reducing clock training time [patent_app_type] => utility [patent_app_number] => 17/581445 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 11838 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17581445 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/581445
Apparatus, memory device, and method reducing clock training time Jan 20, 2022 Issued
Array ( [id] => 17598220 [patent_doc_number] => 20220147794 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-12 [patent_title] => Deep Learning Neural Network Classifier Using Non-volatile Memory Array [patent_app_type] => utility [patent_app_number] => 17/580862 [patent_app_country] => US [patent_app_date] => 2022-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7907 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17580862 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/580862
Deep learning neural network classifier using non-volatile memory array Jan 20, 2022 Issued
Array ( [id] => 18080732 [patent_doc_number] => 20220406344 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-22 [patent_title] => PROGRAMMABLE COLUMN ACCESS [patent_app_type] => utility [patent_app_number] => 17/648403 [patent_app_country] => US [patent_app_date] => 2022-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15355 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17648403 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/648403
Programmable column access Jan 18, 2022 Issued
Array ( [id] => 18890836 [patent_doc_number] => 11869613 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-01-09 [patent_title] => Semiconductor structure and endurance test method using the same [patent_app_type] => utility [patent_app_number] => 17/574629 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2802 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17574629 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/574629
Semiconductor structure and endurance test method using the same Jan 12, 2022 Issued
Array ( [id] => 19820717 [patent_doc_number] => 20250078924 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => DATA PROCESSING METHOD BASED ON MEMRISTOR ARRAY, AND ELECTRONIC APPARATUS [patent_app_type] => utility [patent_app_number] => 18/726931 [patent_app_country] => US [patent_app_date] => 2022-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14951 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18726931 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/726931
DATA PROCESSING METHOD BASED ON MEMRISTOR ARRAY, AND ELECTRONIC APPARATUS Jan 10, 2022 Pending
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