Search

Scott A. Smith

Examiner (ID: 231, Phone: (571)272-4469 , Office: P/3721 )

Most Active Art Unit
3721
Art Unit(s)
3731, 3727, 3204, 3205, 3616, 3721
Total Applications
3908
Issued Applications
3490
Pending Applications
120
Abandoned Applications
330

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20274663 [patent_doc_number] => 12444447 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-14 [patent_title] => Digital phase change memory (PCM) array for analog computing [patent_app_type] => utility [patent_app_number] => 17/565137 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3665 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565137 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565137
Digital phase change memory (PCM) array for analog computing Dec 28, 2021 Issued
Array ( [id] => 17536462 [patent_doc_number] => 20220115071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-14 [patent_title] => TWO-PART PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/555728 [patent_app_country] => US [patent_app_date] => 2021-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17555728 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/555728
Two-part programming of memory cells Dec 19, 2021 Issued
Array ( [id] => 19007421 [patent_doc_number] => 20240071492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => CONTROL DEVICE, STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/270980 [patent_app_country] => US [patent_app_date] => 2021-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9539 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18270980 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/270980
CONTROL DEVICE, STORAGE DEVICE, SEMICONDUCTOR DEVICE, AND CONTROL METHOD Dec 16, 2021 Issued
Array ( [id] => 19494099 [patent_doc_number] => 12112820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-08 [patent_title] => Single event effect mitigation with smart-redundancy [patent_app_type] => utility [patent_app_number] => 17/539923 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 9086 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17539923 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/539923
Single event effect mitigation with smart-redundancy Nov 30, 2021 Issued
Array ( [id] => 18804114 [patent_doc_number] => 11837277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-05 [patent_title] => Dual slc/qlc programming and resource releasing [patent_app_type] => utility [patent_app_number] => 17/455696 [patent_app_country] => US [patent_app_date] => 2021-11-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5396 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17455696 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/455696
Dual slc/qlc programming and resource releasing Nov 18, 2021 Issued
Array ( [id] => 18857032 [patent_doc_number] => 11854623 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods [patent_app_type] => utility [patent_app_number] => 17/520276 [patent_app_country] => US [patent_app_date] => 2021-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 11213 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17520276 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/520276
Memory controller, memory device and memory system having improved threshold voltage distribution characteristics and related operating methods Nov 4, 2021 Issued
Array ( [id] => 17900506 [patent_doc_number] => 20220310168 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => OPERATING METHOD OF STORAGE CONTROLLER USING COUNT VALUE OF DIRECT MEMORY ACCESS, STORAGE DEVICE INCLUDING STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 17/511738 [patent_app_country] => US [patent_app_date] => 2021-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14427 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17511738 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/511738
OPERATING METHOD OF STORAGE CONTROLLER USING COUNT VALUE OF DIRECT MEMORY ACCESS, STORAGE DEVICE INCLUDING STORAGE CONTROLLER, AND OPERATING METHOD OF STORAGE DEVICE Oct 26, 2021 Abandoned
Array ( [id] => 17752490 [patent_doc_number] => 20220230695 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-21 [patent_title] => NONVOLATILE MEMORY DEVICE, MEMORY SYSTEM INCLUDING SAME, AND OPERATING METHOD OF NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/498832 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9473 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17498832 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/498832
Nonvolatile memory device including artificial neural network, memory system including same, and operating method of nonvolatile memory device including artificial neural network Oct 11, 2021 Issued
Array ( [id] => 18312079 [patent_doc_number] => 20230115979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Mitigating Edge Layer Effect In Partially Written Blocks [patent_app_type] => utility [patent_app_number] => 17/499571 [patent_app_country] => US [patent_app_date] => 2021-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5388 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17499571 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/499571
Mitigating edge layer effect in partially written blocks Oct 11, 2021 Issued
Array ( [id] => 18306838 [patent_doc_number] => 20230110738 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => Multibit Memory Device and Method of Operating the Same [patent_app_type] => utility [patent_app_number] => 17/497931 [patent_app_country] => US [patent_app_date] => 2021-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6790 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17497931 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/497931
Multibit memory device and method of operating the same Oct 8, 2021 Issued
Array ( [id] => 18998921 [patent_doc_number] => 11915775 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-02-27 [patent_title] => Apparatuses and methods for bad row mode [patent_app_type] => utility [patent_app_number] => 17/449297 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 8636 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17449297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/449297
Apparatuses and methods for bad row mode Sep 28, 2021 Issued
Array ( [id] => 18239103 [patent_doc_number] => 20230071414 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-09 [patent_title] => SENSE AMPLIFICATION CIRCUIT AND DATA READING METHOD [patent_app_type] => utility [patent_app_number] => 17/773255 [patent_app_country] => US [patent_app_date] => 2021-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17773255 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/773255
SENSE AMPLIFICATION CIRCUIT AND DATA READING METHOD Sep 23, 2021 Abandoned
Array ( [id] => 17318512 [patent_doc_number] => 20210407562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-30 [patent_title] => PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY [patent_app_type] => utility [patent_app_number] => 17/473615 [patent_app_country] => US [patent_app_date] => 2021-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28699 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17473615 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/473615
PERFORMING LOGICAL OPERATIONS USING SENSING CIRCUITRY Sep 12, 2021 Abandoned
Array ( [id] => 18688131 [patent_doc_number] => 11783874 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-10 [patent_title] => Memory with swap mode [patent_app_type] => utility [patent_app_number] => 17/470579 [patent_app_country] => US [patent_app_date] => 2021-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 11030 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17470579 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/470579
Memory with swap mode Sep 8, 2021 Issued
Array ( [id] => 18721293 [patent_doc_number] => 11798645 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Storage device for performing reliability check by using error correction code (ECC) data [patent_app_type] => utility [patent_app_number] => 17/467968 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11036 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467968 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467968
Storage device for performing reliability check by using error correction code (ECC) data Sep 6, 2021 Issued
Array ( [id] => 18131145 [patent_doc_number] => 11557360 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-01-17 [patent_title] => Memory test circuit and device wafer [patent_app_type] => utility [patent_app_number] => 17/467878 [patent_app_country] => US [patent_app_date] => 2021-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8973 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17467878 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/467878
Memory test circuit and device wafer Sep 6, 2021 Issued
Array ( [id] => 18548049 [patent_doc_number] => 11721407 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-08 [patent_title] => BIST for performing parallel and serial test on memories [patent_app_type] => utility [patent_app_number] => 17/463937 [patent_app_country] => US [patent_app_date] => 2021-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 8697 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17463937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/463937
BIST for performing parallel and serial test on memories Aug 31, 2021 Issued
Array ( [id] => 17401668 [patent_doc_number] => 20220043758 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-02-10 [patent_title] => LOW LATENCY MEMORY ACCESS [patent_app_type] => utility [patent_app_number] => 17/461064 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10348 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461064 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461064
Low latency memory access Aug 29, 2021 Issued
Array ( [id] => 17886173 [patent_doc_number] => 20220301650 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-22 [patent_title] => CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE CONTROLLER [patent_app_type] => utility [patent_app_number] => 17/461749 [patent_app_country] => US [patent_app_date] => 2021-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13602 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17461749 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/461749
CONTROLLER CONTROLLING SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE CONTROLLER Aug 29, 2021 Abandoned
Array ( [id] => 18235788 [patent_doc_number] => 11600352 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-03-07 [patent_title] => Storage device [patent_app_type] => utility [patent_app_number] => 17/459807 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459807 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459807
Storage device Aug 26, 2021 Issued
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