Search

Scott B. Geyer

Examiner (ID: 4423, Phone: (571)272-1958 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 4113, 2813, 2829
Total Applications
1969
Issued Applications
1784
Pending Applications
107
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6679685 [patent_doc_number] => 20030229826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-12-11 [patent_title] => 'Data storage system using 3-party hand-off protocol to facilitate failure recovery' [patent_app_type] => new [patent_app_number] => 10/166975 [patent_app_country] => US [patent_app_date] => 2002-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8566 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0229/20030229826.pdf [firstpage_image] =>[orig_patent_app_number] => 10166975 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/166975
Data storage system using 3-party hand-off protocol to facilitate failure recovery Jun 9, 2002 Issued
Array ( [id] => 786121 [patent_doc_number] => 06993684 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-01-31 [patent_title] => 'Ring control node' [patent_app_type] => utility [patent_app_number] => 10/164509 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4669 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/993/06993684.pdf [firstpage_image] =>[orig_patent_app_number] => 10164509 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164509
Ring control node Jun 5, 2002 Issued
Array ( [id] => 749567 [patent_doc_number] => 07032133 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-18 [patent_title] => 'Method and system for testing a computing arrangement' [patent_app_type] => utility [patent_app_number] => 10/164877 [patent_app_country] => US [patent_app_date] => 2002-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8797 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/032/07032133.pdf [firstpage_image] =>[orig_patent_app_number] => 10164877 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164877
Method and system for testing a computing arrangement Jun 5, 2002 Issued
Array ( [id] => 771545 [patent_doc_number] => 07010724 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-03-07 [patent_title] => 'Operating system hang detection and methods for handling hang conditions' [patent_app_type] => utility [patent_app_number] => 10/164456 [patent_app_country] => US [patent_app_date] => 2002-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4298 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 36 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/010/07010724.pdf [firstpage_image] =>[orig_patent_app_number] => 10164456 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/164456
Operating system hang detection and methods for handling hang conditions Jun 4, 2002 Issued
Array ( [id] => 873753 [patent_doc_number] => 07366951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-29 [patent_title] => 'Method and apparatus for test program generation based on an instruction set description of a processor' [patent_app_type] => utility [patent_app_number] => 10/155801 [patent_app_country] => US [patent_app_date] => 2002-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4578 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/366/07366951.pdf [firstpage_image] =>[orig_patent_app_number] => 10155801 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/155801
Method and apparatus for test program generation based on an instruction set description of a processor May 23, 2002 Issued
Array ( [id] => 388735 [patent_doc_number] => 07305589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-12-04 [patent_title] => 'Memory card and its initial setting method' [patent_app_type] => utility [patent_app_number] => 10/484043 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4782 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/305/07305589.pdf [firstpage_image] =>[orig_patent_app_number] => 10484043 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/484043
Memory card and its initial setting method May 7, 2002 Issued
Array ( [id] => 1007738 [patent_doc_number] => 06907549 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Error detection in communication systems' [patent_app_type] => utility [patent_app_number] => 10/109949 [patent_app_country] => US [patent_app_date] => 2002-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5188 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/907/06907549.pdf [firstpage_image] =>[orig_patent_app_number] => 10109949 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/109949
Error detection in communication systems Mar 28, 2002 Issued
Array ( [id] => 753367 [patent_doc_number] => 07028228 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-04-11 [patent_title] => 'Method and apparatus for identifying problems in computer networks' [patent_app_type] => utility [patent_app_number] => 10/108962 [patent_app_country] => US [patent_app_date] => 2002-03-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 20012 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/028/07028228.pdf [firstpage_image] =>[orig_patent_app_number] => 10108962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108962
Method and apparatus for identifying problems in computer networks Mar 27, 2002 Issued
Array ( [id] => 958241 [patent_doc_number] => 06957363 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-10-18 [patent_title] => 'Method and apparatus for controlling the termination of processes in response to a shutdown command' [patent_app_type] => utility [patent_app_number] => 10/108053 [patent_app_country] => US [patent_app_date] => 2002-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2467 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/957/06957363.pdf [firstpage_image] =>[orig_patent_app_number] => 10108053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/108053
Method and apparatus for controlling the termination of processes in response to a shutdown command Mar 26, 2002 Issued
Array ( [id] => 7618398 [patent_doc_number] => 06944795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-13 [patent_title] => 'Method and apparatus for stabilizing GUI testing' [patent_app_type] => utility [patent_app_number] => 10/105919 [patent_app_country] => US [patent_app_date] => 2002-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4273 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/944/06944795.pdf [firstpage_image] =>[orig_patent_app_number] => 10105919 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/105919
Method and apparatus for stabilizing GUI testing Mar 24, 2002 Issued
Array ( [id] => 6831540 [patent_doc_number] => 20030182598 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Systems and methods for monitoring object activity through an external agent using a proxy object' [patent_app_type] => new [patent_app_number] => 10/105066 [patent_app_country] => US [patent_app_date] => 2002-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4376 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0182/20030182598.pdf [firstpage_image] =>[orig_patent_app_number] => 10105066 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/105066
Systems and methods for monitoring object activity through an external agent using a proxy object Mar 21, 2002 Issued
Array ( [id] => 6661143 [patent_doc_number] => 20030135787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method and system using hardware assistance for continuance of trap mode during or after interruption sequences' [patent_app_type] => new [patent_app_number] => 10/045513 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11443 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135787.pdf [firstpage_image] =>[orig_patent_app_number] => 10045513 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045513
Method and system using hardware assistance for continuance of trap mode during or after interruption sequences Jan 13, 2002 Issued
Array ( [id] => 6661145 [patent_doc_number] => 20030135789 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Method and system for instruction tracing with enhanced interrupt avoidance' [patent_app_type] => new [patent_app_number] => 10/045307 [patent_app_country] => US [patent_app_date] => 2002-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 12757 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20030135789.pdf [firstpage_image] =>[orig_patent_app_number] => 10045307 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045307
Method and system for instruction tracing with enhanced interrupt avoidance Jan 13, 2002 Issued
Array ( [id] => 1004765 [patent_doc_number] => 06910160 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-21 [patent_title] => 'System, method, and computer program product for preserving trace data after partition crash in logically partitioned systems' [patent_app_type] => utility [patent_app_number] => 10/045281 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4042 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/910/06910160.pdf [firstpage_image] =>[orig_patent_app_number] => 10045281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045281
System, method, and computer program product for preserving trace data after partition crash in logically partitioned systems Jan 9, 2002 Issued
Array ( [id] => 6857778 [patent_doc_number] => 20030131279 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-10 [patent_title] => 'System, method, and computer program product for preventing machine crashes due to hard errors in logically partitioned systems' [patent_app_type] => new [patent_app_number] => 10/045280 [patent_app_country] => US [patent_app_date] => 2002-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4201 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20030131279.pdf [firstpage_image] =>[orig_patent_app_number] => 10045280 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/045280
System, method, and computer program product for preventing machine crashes due to hard errors in logically partitioned systems Jan 9, 2002 Issued
Array ( [id] => 6793464 [patent_doc_number] => 20030088808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-08 [patent_title] => 'Design verification' [patent_app_type] => new [patent_app_number] => 10/007625 [patent_app_country] => US [patent_app_date] => 2001-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6312 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20030088808.pdf [firstpage_image] =>[orig_patent_app_number] => 10007625 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/007625
System design verification using selected states of a processor-based system to reveal deficiencies Nov 1, 2001 Issued
Array ( [id] => 5990835 [patent_doc_number] => 20020099973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-07-25 [patent_title] => 'Fault tolerance for computer programs that operate over a communication network' [patent_app_type] => new [patent_app_number] => 10/053240 [patent_app_country] => US [patent_app_date] => 2001-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 7141 [patent_no_of_claims] => 111 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20020099973.pdf [firstpage_image] =>[orig_patent_app_number] => 10053240 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/053240
Fault tolerance for computer programs that operate over a communication network Oct 25, 2001 Issued
Array ( [id] => 486016 [patent_doc_number] => 07225369 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-29 [patent_title] => 'Device for monitoring a processor' [patent_app_type] => utility [patent_app_number] => 10/416766 [patent_app_country] => US [patent_app_date] => 2001-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2706 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/225/07225369.pdf [firstpage_image] =>[orig_patent_app_number] => 10416766 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/416766
Device for monitoring a processor Oct 15, 2001 Issued
Array ( [id] => 6839944 [patent_doc_number] => 20030037284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-02-20 [patent_title] => 'Self-monitoring mechanism in fault-tolerant distributed dynamic network systems' [patent_app_type] => new [patent_app_number] => 09/963687 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6025 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 35 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20030037284.pdf [firstpage_image] =>[orig_patent_app_number] => 09963687 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/963687
Self-monitoring mechanism in fault-tolerant distributed dynamic network systems Sep 26, 2001 Abandoned
Array ( [id] => 6675937 [patent_doc_number] => 20030061540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-03-27 [patent_title] => 'Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system' [patent_app_type] => new [patent_app_number] => 09/965000 [patent_app_country] => US [patent_app_date] => 2001-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 5716 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20030061540.pdf [firstpage_image] =>[orig_patent_app_number] => 09965000 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/965000
Method and apparatus for verifying hardware implementation of a processor architecture in a logically partitioned data processing system Sep 26, 2001 Issued
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