Search

Scott B. Geyer

Examiner (ID: 3879, Phone: (571)272-1958 , Office: P/2812 )

Most Active Art Unit
2812
Art Unit(s)
2812, 2829, 2813, 4113
Total Applications
1967
Issued Applications
1781
Pending Applications
109
Abandoned Applications
105

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4782610 [patent_doc_number] => 20080135939 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-12 [patent_title] => 'Fabrication method of semiconductor package and structure thereof' [patent_app_type] => utility [patent_app_number] => 12/000021 [patent_app_country] => US [patent_app_date] => 2007-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3322 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0135/20080135939.pdf [firstpage_image] =>[orig_patent_app_number] => 12000021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/000021
Fabrication method of semiconductor package and structure thereof Dec 6, 2007 Abandoned
Array ( [id] => 4485567 [patent_doc_number] => 07883925 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Image sensor and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/947496 [patent_app_country] => US [patent_app_date] => 2007-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2753 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883925.pdf [firstpage_image] =>[orig_patent_app_number] => 11947496 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/947496
Image sensor and method for fabricating the same Nov 28, 2007 Issued
Array ( [id] => 5561645 [patent_doc_number] => 20090134497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Through Substrate Via Semiconductor Components' [patent_app_type] => utility [patent_app_number] => 11/944846 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 7331 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134497.pdf [firstpage_image] =>[orig_patent_app_number] => 11944846 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944846
Through substrate via semiconductor components Nov 25, 2007 Issued
Array ( [id] => 5561659 [patent_doc_number] => 20090134511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-28 [patent_title] => 'Multiple Size Package Socket' [patent_app_type] => utility [patent_app_number] => 11/944625 [patent_app_country] => US [patent_app_date] => 2007-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4128 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20090134511.pdf [firstpage_image] =>[orig_patent_app_number] => 11944625 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/944625
Multiple size package socket Nov 24, 2007 Issued
Array ( [id] => 4513795 [patent_doc_number] => 07910387 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Phosphor coating method for fabricating light emitting semiconductor device and applications thereof' [patent_app_type] => utility [patent_app_number] => 11/984775 [patent_app_country] => US [patent_app_date] => 2007-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 4148 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/910/07910387.pdf [firstpage_image] =>[orig_patent_app_number] => 11984775 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/984775
Phosphor coating method for fabricating light emitting semiconductor device and applications thereof Nov 20, 2007 Issued
Array ( [id] => 4922024 [patent_doc_number] => 20080070339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-20 [patent_title] => 'Method for one-way coupling an input signal to an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/985541 [patent_app_country] => US [patent_app_date] => 2007-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6066 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20080070339.pdf [firstpage_image] =>[orig_patent_app_number] => 11985541 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/985541
Method for one-way coupling an input signal to an integrated circuit Nov 14, 2007 Issued
Array ( [id] => 32541 [patent_doc_number] => 07790586 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-07 [patent_title] => 'Plasma doping method' [patent_app_type] => utility [patent_app_number] => 12/158852 [patent_app_country] => US [patent_app_date] => 2007-11-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 15622 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/790/07790586.pdf [firstpage_image] =>[orig_patent_app_number] => 12158852 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/158852
Plasma doping method Nov 12, 2007 Issued
Array ( [id] => 4464275 [patent_doc_number] => 07935632 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-03 [patent_title] => 'Reduced metal pipe formation in metal silicide contacts' [patent_app_type] => utility [patent_app_number] => 11/935415 [patent_app_country] => US [patent_app_date] => 2007-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2644 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/935/07935632.pdf [firstpage_image] =>[orig_patent_app_number] => 11935415 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/935415
Reduced metal pipe formation in metal silicide contacts Nov 5, 2007 Issued
Array ( [id] => 4514943 [patent_doc_number] => 07932131 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-04-26 [patent_title] => 'Reduction of package height in a stacked die configuration' [patent_app_type] => utility [patent_app_number] => 11/983041 [patent_app_country] => US [patent_app_date] => 2007-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 4013 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/932/07932131.pdf [firstpage_image] =>[orig_patent_app_number] => 11983041 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/983041
Reduction of package height in a stacked die configuration Nov 4, 2007 Issued
Array ( [id] => 4568564 [patent_doc_number] => 07858446 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Sensor-type semiconductor package and fabrication method thereof' [patent_app_type] => utility [patent_app_number] => 11/982516 [patent_app_country] => US [patent_app_date] => 2007-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 17 [patent_no_of_words] => 4361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 191 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/858/07858446.pdf [firstpage_image] =>[orig_patent_app_number] => 11982516 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/982516
Sensor-type semiconductor package and fabrication method thereof Nov 1, 2007 Issued
Array ( [id] => 4749307 [patent_doc_number] => 20080157378 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-07-03 [patent_title] => 'SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SAME' [patent_app_type] => utility [patent_app_number] => 11/933901 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2135 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20080157378.pdf [firstpage_image] =>[orig_patent_app_number] => 11933901 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933901
SEMICONDUCTOR DEVICE, AND METHOD OF MANUFACTURING SAME Oct 31, 2007 Abandoned
Array ( [id] => 4958875 [patent_doc_number] => 20080273299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-11-06 [patent_title] => 'Memory card and method for fabricating the same' [patent_app_type] => utility [patent_app_number] => 11/981216 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4194 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20080273299.pdf [firstpage_image] =>[orig_patent_app_number] => 11981216 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/981216
Memory card and method for fabricating the same Oct 30, 2007 Issued
Array ( [id] => 4433 [patent_doc_number] => 07811903 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-12 [patent_title] => 'Thin flip-chip method' [patent_app_type] => utility [patent_app_number] => 11/923832 [patent_app_country] => US [patent_app_date] => 2007-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 9380 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/811/07811903.pdf [firstpage_image] =>[orig_patent_app_number] => 11923832 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/923832
Thin flip-chip method Oct 24, 2007 Issued
Array ( [id] => 6352787 [patent_doc_number] => 20100022089 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-01-28 [patent_title] => 'Method for manufacturing semiconductor device using quadruple-layer laminate' [patent_app_type] => utility [patent_app_number] => 12/311742 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30418 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20100022089.pdf [firstpage_image] =>[orig_patent_app_number] => 12311742 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/311742
Method for manufacturing semiconductor device using quadruple-layer laminate Oct 11, 2007 Issued
Array ( [id] => 5449896 [patent_doc_number] => 20090065932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-12 [patent_title] => 'Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby' [patent_app_type] => utility [patent_app_number] => 11/853752 [patent_app_country] => US [patent_app_date] => 2007-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3102 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20090065932.pdf [firstpage_image] =>[orig_patent_app_number] => 11853752 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/853752
Methods of forming nano-coatings for improved adhesion between first level interconnects and epoxy under-fills in microelectronic packages and structures formed thereby Sep 10, 2007 Issued
Array ( [id] => 5319860 [patent_doc_number] => 20090057850 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Surface Mountable Semiconductor Package with Solder Bonding Features' [patent_app_type] => utility [patent_app_number] => 11/850526 [patent_app_country] => US [patent_app_date] => 2007-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2927 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057850.pdf [firstpage_image] =>[orig_patent_app_number] => 11850526 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/850526
Surface mountable semiconductor package with solder bonding features Sep 4, 2007 Issued
Array ( [id] => 5319933 [patent_doc_number] => 20090057923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Methods of Fabricating Semiconductor Devices and Structures Thereof' [patent_app_type] => utility [patent_app_number] => 11/849535 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6133 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057923.pdf [firstpage_image] =>[orig_patent_app_number] => 11849535 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849535
Methods of fabricating semiconductor devices and structures thereof Sep 3, 2007 Issued
Array ( [id] => 5319938 [patent_doc_number] => 20090057928 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'Semiconductor Chip with Stratified Underfill' [patent_app_type] => utility [patent_app_number] => 11/849545 [patent_app_country] => US [patent_app_date] => 2007-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4126 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0057/20090057928.pdf [firstpage_image] =>[orig_patent_app_number] => 11849545 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/849545
Semiconductor chip with stratified underfill Sep 3, 2007 Issued
Array ( [id] => 5307578 [patent_doc_number] => 20090014859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-01-15 [patent_title] => 'INTERCONNECTS FOR PACKAGED SEMICONDUCTOR DEVICES AND METHODS FOR MANUFACTURING SUCH DEVICES' [patent_app_type] => utility [patent_app_number] => 11/848836 [patent_app_country] => US [patent_app_date] => 2007-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5009 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20090014859.pdf [firstpage_image] =>[orig_patent_app_number] => 11848836 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/848836
Interconnects for packaged semiconductor devices and methods for manufacturing such devices Aug 30, 2007 Issued
Array ( [id] => 5321547 [patent_doc_number] => 20090059537 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-03-05 [patent_title] => 'OPTIMIZATION OF ELECTRONIC PACKAGE GEOMETRY FOR THERMAL DISSIPATION' [patent_app_type] => utility [patent_app_number] => 11/847716 [patent_app_country] => US [patent_app_date] => 2007-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1561 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0059/20090059537.pdf [firstpage_image] =>[orig_patent_app_number] => 11847716 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/847716
Optimization of electronic package geometry for thermal dissipation Aug 29, 2007 Issued
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