Scott Cummings

Array ( [id] => 20181262 [patent_doc_number] => 20250265220 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => MULTI-CHIP MODULE PACKAGE TECHNOLOGY FOR ADVANCED DRIVER ASSISTANCE SYSTEM APPLICATION [patent_app_type] => utility [patent_app_number] => 19/053229 [patent_app_country] => US [patent_app_date] => 2025-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19053229 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20181124 [patent_doc_number] => 20250265082 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-21 [patent_title] => COMPUTATION ENGINE WITH SPARSE MATRIX INSTRUCTION [patent_app_type] => utility [patent_app_number] => 19/052786 [patent_app_country] => US [patent_app_date] => 2025-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9166 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19052786 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20000811 [patent_doc_number] => 20250139033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => MEMORY CHIP AND MEMORY SYSTEM WITH THE SAME [patent_app_type] => utility [patent_app_number] => 19/008669 [patent_app_country] => US [patent_app_date] => 2025-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19008669 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20061641 [patent_doc_number] => 20250199863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION [patent_app_type] => utility [patent_app_number] => 18/958384 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 46868 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18958384 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19849030 [patent_doc_number] => 20250094381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations [patent_app_type] => utility [patent_app_number] => 18/959080 [patent_app_country] => US [patent_app_date] => 2024-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16019 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18959080 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20035080 [patent_doc_number] => 20250173302 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-29 [patent_title] => VIRTUAL INTERFACE TEST FOR A COMPUTE EXPRESS LINK COMPLIANT MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/957370 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4819 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18957370 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19748008 [patent_doc_number] => 20250036573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => METHODS AND APPARATUS FOR READ-MODIFY-WRITE SUPPORT IN MULTI-BANKED DATA RAM CACHE FOR BANK ARBITRATION [patent_app_type] => utility [patent_app_number] => 18/914845 [patent_app_country] => US [patent_app_date] => 2024-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 95377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18914845 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19864758 [patent_doc_number] => 20250103544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-27 [patent_title] => METHOD, APPARATUS, DEVICE, AND STORAGE MEDIUM FOR RESOURCE CONFIGURATION [patent_app_type] => utility [patent_app_number] => 18/898354 [patent_app_country] => US [patent_app_date] => 2024-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6496 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18898354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19660457 [patent_doc_number] => 20240427522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/829179 [patent_app_country] => US [patent_app_date] => 2024-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20054 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18829179 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20731979 [patent_doc_number] => 12639237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Memory device with internal processing interface [patent_app_type] => utility [patent_app_number] => 18/819544 [patent_app_country] => US [patent_app_date] => 2024-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 5764 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18819544 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20311726 [patent_doc_number] => 20250329355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => SYSTEMS AND METHODS FOR DATA SYNCHRONIZATION [patent_app_type] => utility [patent_app_number] => 18/805418 [patent_app_country] => US [patent_app_date] => 2024-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7488 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18805418 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19617556 [patent_doc_number] => 20240403236 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-05 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/802751 [patent_app_country] => US [patent_app_date] => 2024-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14588 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18802751 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19588419 [patent_doc_number] => 20240385976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => DATA TRANSMISSION POWER OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/785748 [patent_app_country] => US [patent_app_date] => 2024-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5013 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18785748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20797425 [patent_doc_number] => 20260178328 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-06-25 [patent_title] => INSTRUCTION GENERATION APPARATUS AND METHOD, DEVICE, STORAGE MEDIUM, AND COMPUTER PROGRAM PRODUCT [patent_app_type] => utility [patent_app_number] => 18/832283 [patent_app_country] => US [patent_app_date] => 2023-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6317 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18832283 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19468829 [patent_doc_number] => 20240322499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => SYSTEMS, DEVICES, AND METHODS FOR CONNECTORS [patent_app_type] => utility [patent_app_number] => 18/732874 [patent_app_country] => US [patent_app_date] => 2024-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4189 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18732874 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19466499 [patent_doc_number] => 20240320169 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => DELAY ELEMENTS FOR COMMAND TIMING IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/731979 [patent_app_country] => US [patent_app_date] => 2024-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7833 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18731979 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20446909 [patent_doc_number] => 20260003631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => Out-Of-Order Unit Stride Data Prefetcher with Scoreboarding [patent_app_type] => utility [patent_app_number] => 18/652253 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4879 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 227 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652253 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19514286 [patent_doc_number] => 20240345972 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => METHODS, DEVICES AND SYSTEMS FOR HIGH SPEED TRANSACTIONS WITH NONVOLATILE MEMORY ON A DOUBLE DATA RATE MEMORY BUS [patent_app_type] => utility [patent_app_number] => 18/647048 [patent_app_country] => US [patent_app_date] => 2024-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10100 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18647048 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19383171 [patent_doc_number] => 20240273041 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-15 [patent_title] => DEVICES USING CHIPLET BASED STORAGE ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/643881 [patent_app_country] => US [patent_app_date] => 2024-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18643881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19362936 [patent_doc_number] => 20240264970 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => REMOTE MEMORY BRIDGE AND METHOD FOR OPERATION [patent_app_type] => utility [patent_app_number] => 18/640868 [patent_app_country] => US [patent_app_date] => 2024-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18640868 [rel_patent_id] =>[rel_patent_doc_number] =>)