Search

Scott Cummings

Examiner (ID: 18991)

Most Active Art Unit
2406
Art Unit(s)
2406, 3108, 3626, 2899
Total Applications
704
Issued Applications
586
Pending Applications
5
Abandoned Applications
113

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19949939 [patent_doc_number] => 12321301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2025-06-03 [patent_title] => Low-latency packet processing for network device [patent_app_type] => utility [patent_app_number] => 17/891200 [patent_app_country] => US [patent_app_date] => 2022-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 18 [patent_no_of_words] => 8244 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17891200 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/891200
Low-latency packet processing for network device Aug 18, 2022 Issued
Array ( [id] => 18592117 [patent_doc_number] => 11741015 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-08-29 [patent_title] => Fault buffer for tracking page faults in unified virtual memory system [patent_app_type] => utility [patent_app_number] => 17/820870 [patent_app_country] => US [patent_app_date] => 2022-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13075 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17820870 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/820870
Fault buffer for tracking page faults in unified virtual memory system Aug 17, 2022 Issued
Array ( [id] => 20000829 [patent_doc_number] => 20250139051 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => GLOBALS BLOCKS IN REPLICATED BLOCK ARRAYS [patent_app_type] => utility [patent_app_number] => 18/683636 [patent_app_country] => US [patent_app_date] => 2022-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18683636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/683636
GLOBALS BLOCKS IN REPLICATED BLOCK ARRAYS Aug 10, 2022 Pending
Array ( [id] => 18022883 [patent_doc_number] => 20220374382 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => METHOD AND APPARATUS FOR EXTENDING I3C CAPABILITY ACROSS MULTIPLE PLATFORMS AND DEVICES OVER USB-C CONNECTION [patent_app_type] => utility [patent_app_number] => 17/882462 [patent_app_country] => US [patent_app_date] => 2022-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -23 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17882462 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/882462
METHOD AND APPARATUS FOR EXTENDING I3C CAPABILITY ACROSS MULTIPLE PLATFORMS AND DEVICES OVER USB-C CONNECTION Aug 4, 2022 Pending
Array ( [id] => 18644714 [patent_doc_number] => 11768782 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-26 [patent_title] => Data bus duty cycle distortion compensation [patent_app_type] => utility [patent_app_number] => 17/880226 [patent_app_country] => US [patent_app_date] => 2022-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17880226 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/880226
Data bus duty cycle distortion compensation Aug 2, 2022 Issued
Array ( [id] => 19725912 [patent_doc_number] => 20250028663 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => SYSTEM, METHOD, DEVICE, PROCESSOR, AND STORAGE MEDIUM THEREOF FOR IMPLEMENTING LARGE-SCALE FIFO DATA PROCESSING BASED ON DDR [patent_app_type] => utility [patent_app_number] => 18/714500 [patent_app_country] => US [patent_app_date] => 2022-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5090 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18714500 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/714500
SYSTEM, METHOD, DEVICE, PROCESSOR, AND STORAGE MEDIUM THEREOF FOR IMPLEMENTING LARGE-SCALE FIFO DATA PROCESSING BASED ON DDR Jul 20, 2022 Pending
Array ( [id] => 17984739 [patent_doc_number] => 20220350776 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-03 [patent_title] => Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector Operations [patent_app_type] => utility [patent_app_number] => 17/869617 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15969 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869617 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869617
Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Jul 19, 2022 Issued
Array ( [id] => 19652999 [patent_doc_number] => 12174785 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-12-24 [patent_title] => Coprocessors with bypass optimization, variable grid architecture, and fused vector operations [patent_app_type] => utility [patent_app_number] => 17/869620 [patent_app_country] => US [patent_app_date] => 2022-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 19 [patent_no_of_words] => 15970 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17869620 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/869620
Coprocessors with bypass optimization, variable grid architecture, and fused vector operations Jul 19, 2022 Issued
Array ( [id] => 18111627 [patent_doc_number] => 20230004507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => COMMUNICATING DATA WITH STACKED MEMORY DIES [patent_app_type] => utility [patent_app_number] => 17/864023 [patent_app_country] => US [patent_app_date] => 2022-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39165 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17864023 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/864023
Communicating data with stacked memory dies Jul 12, 2022 Issued
Array ( [id] => 18592140 [patent_doc_number] => 11741038 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2023-08-29 [patent_title] => Method, server system, and non-transitory computer readable medium for hot plugging [patent_app_type] => utility [patent_app_number] => 17/854292 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3061 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17854292 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/854292
Method, server system, and non-transitory computer readable medium for hot plugging Jun 29, 2022 Issued
Array ( [id] => 19764600 [patent_doc_number] => 12222890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Programmable logic device configuration over communication fabrics [patent_app_type] => utility [patent_app_number] => 17/846305 [patent_app_country] => US [patent_app_date] => 2022-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17846305 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/846305
Programmable logic device configuration over communication fabrics Jun 21, 2022 Issued
Array ( [id] => 19499203 [patent_doc_number] => 20240338221 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-10 [patent_title] => Debug In System On A Chip With Securely Partitioned Memory Space [patent_app_type] => utility [patent_app_number] => 18/577677 [patent_app_country] => US [patent_app_date] => 2022-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18577677 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/577677
Debug in system on a chip with securely partitioned memory space Jun 2, 2022 Issued
Array ( [id] => 18022884 [patent_doc_number] => 20220374383 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => TRANSACTION MAPPING MODULE [patent_app_type] => utility [patent_app_number] => 17/750135 [patent_app_country] => US [patent_app_date] => 2022-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4773 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17750135 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/750135
TRANSACTION MAPPING MODULE May 19, 2022 Abandoned
Array ( [id] => 17992957 [patent_doc_number] => 20220358994 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-10 [patent_title] => Termination for Single-Ended Mode [patent_app_type] => utility [patent_app_number] => 17/662325 [patent_app_country] => US [patent_app_date] => 2022-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -37 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17662325 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/662325
Termination for single-ended mode May 5, 2022 Issued
Array ( [id] => 20317293 [patent_doc_number] => 12455844 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-28 [patent_title] => IO request scheduling methods and apparatuses [patent_app_type] => utility [patent_app_number] => 18/553145 [patent_app_country] => US [patent_app_date] => 2022-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3100 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18553145 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/553145
IO request scheduling methods and apparatuses Apr 5, 2022 Issued
Array ( [id] => 19062192 [patent_doc_number] => 11941428 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-03-26 [patent_title] => Ensuring transactional ordering in I/O agent [patent_app_type] => utility [patent_app_number] => 17/657506 [patent_app_country] => US [patent_app_date] => 2022-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 20 [patent_no_of_words] => 19977 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17657506 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/657506
Ensuring transactional ordering in I/O agent Mar 30, 2022 Issued
Array ( [id] => 17706792 [patent_doc_number] => 20220206798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-30 [patent_title] => SCHEDULER QUEUE ASSIGNMENT [patent_app_type] => utility [patent_app_number] => 17/698955 [patent_app_country] => US [patent_app_date] => 2022-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6078 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17698955 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/698955
SCHEDULER QUEUE ASSIGNMENT Mar 17, 2022 Abandoned
Array ( [id] => 19212309 [patent_doc_number] => 12001371 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-04 [patent_title] => Connection of input and / or output modules to a fieldbus with a higher-level controller [patent_app_type] => utility [patent_app_number] => 17/690820 [patent_app_country] => US [patent_app_date] => 2022-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5352 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17690820 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/690820
Connection of input and / or output modules to a fieldbus with a higher-level controller Mar 8, 2022 Issued
Array ( [id] => 19458966 [patent_doc_number] => 12099455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-24 [patent_title] => Memory device with internal processing interface [patent_app_type] => utility [patent_app_number] => 17/591928 [patent_app_country] => US [patent_app_date] => 2022-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10246 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17591928 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/591928
Memory device with internal processing interface Feb 2, 2022 Issued
Array ( [id] => 19092872 [patent_doc_number] => 11954326 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Memory device instantiation onto communication fabrics [patent_app_type] => utility [patent_app_number] => 17/575062 [patent_app_country] => US [patent_app_date] => 2022-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 15784 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17575062 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/575062
Memory device instantiation onto communication fabrics Jan 12, 2022 Issued
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