
Scott Cummings
Examiner (ID: 18991)
| Most Active Art Unit | 2406 |
| Art Unit(s) | 2406, 3108, 3626, 2899 |
| Total Applications | 704 |
| Issued Applications | 586 |
| Pending Applications | 5 |
| Abandoned Applications | 113 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19062168
[patent_doc_number] => 11941404
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-03-26
[patent_title] => Processor and method for controlling the processor
[patent_app_type] => utility
[patent_app_number] => 17/375574
[patent_app_country] => US
[patent_app_date] => 2021-07-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 22
[patent_no_of_words] => 15665
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17375574
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/375574 | Processor and method for controlling the processor | Jul 13, 2021 | Issued |
Array
(
[id] => 17447367
[patent_doc_number] => 20220067872
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => GRAPHICS PROCESSING UNIT INCLUDING DELEGATOR AND OPERATING METHOD THEREOF
[patent_app_type] => utility
[patent_app_number] => 17/372851
[patent_app_country] => US
[patent_app_date] => 2021-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 10871
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372851
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/372851 | Graphics processing unit including delegator and operating method thereof | Jul 11, 2021 | Issued |
Array
(
[id] => 18262177
[patent_doc_number] => 11609879
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-03-21
[patent_title] => Techniques for configuring parallel processors for different application domains
[patent_app_type] => utility
[patent_app_number] => 17/365315
[patent_app_country] => US
[patent_app_date] => 2021-07-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 15
[patent_no_of_words] => 16581
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 96
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365315
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/365315 | Techniques for configuring parallel processors for different application domains | Jun 30, 2021 | Issued |
Array
(
[id] => 18925529
[patent_doc_number] => 20240028533
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-01-25
[patent_title] => AUTOMATED DESIGN OF BEHAVIORAL-BASED DATA MOVERS FOR FIELD PROGRAMMABLE GATE ARRAYS OR OTHER LOGIC DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/364481
[patent_app_country] => US
[patent_app_date] => 2021-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13535
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17364481
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/364481 | Automated design of behavioral-based data movers for field programmable gate arrays or other logic devices | Jun 29, 2021 | Issued |
Array
(
[id] => 17172611
[patent_doc_number] => 20210326281
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-10-21
[patent_title] => APPARATUS AND METHODS FOR IN DATA PATH COMPUTE OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/360388
[patent_app_country] => US
[patent_app_date] => 2021-06-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 25760
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17360388
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/360388 | Apparatus and methods for in data path compute operations | Jun 27, 2021 | Issued |
Array
(
[id] => 18662492
[patent_doc_number] => 20230308514
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-09-28
[patent_title] => INPUT UNIT, CONTROL SYSTEM, COMMUNICATION METHOD, AND RECORDING MEDIUM
[patent_app_type] => utility
[patent_app_number] => 18/035517
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9648
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -5
[patent_words_short_claim] => 181
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18035517
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/035517 | INPUT UNIT, CONTROL SYSTEM, COMMUNICATION METHOD, AND RECORDING MEDIUM | Jun 24, 2021 | Abandoned |
Array
(
[id] => 18095583
[patent_doc_number] => 20220413924
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-29
[patent_title] => USING SPARSITY METADATA TO REDUCE SYSTOLIC ARRAY POWER CONSUMPTION
[patent_app_type] => utility
[patent_app_number] => 17/358542
[patent_app_country] => US
[patent_app_date] => 2021-06-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 51858
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17358542
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/358542 | Using sparsity metadata to reduce systolic array power consumption | Jun 24, 2021 | Issued |
Array
(
[id] => 17597790
[patent_doc_number] => 20220147364
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-12
[patent_title] => SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM
[patent_app_type] => utility
[patent_app_number] => 17/338870
[patent_app_country] => US
[patent_app_date] => 2021-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5980
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 58
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338870
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/338870 | SERVER BASEBOARD, SERVER, CONTROL METHOD, ELECTRONIC APPARATUS AND READABLE MEDIUM | Jun 3, 2021 | Abandoned |
Array
(
[id] => 17581708
[patent_doc_number] => 20220138563
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => METHOD AND DEVICE WITH DEEP LEARNING OPERATIONS
[patent_app_type] => utility
[patent_app_number] => 17/338102
[patent_app_country] => US
[patent_app_date] => 2021-06-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11781
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -25
[patent_words_short_claim] => 69
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17338102
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/338102 | METHOD AND DEVICE WITH DEEP LEARNING OPERATIONS | Jun 2, 2021 | Pending |
Array
(
[id] => 17098956
[patent_doc_number] => 20210286747
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-16
[patent_title] => SYSTEMS AND METHODS FOR SUPPORTING INTER-CHASSIS MANAGEABILITY OF NVME OVER FABRICS BASED SYSTEMS
[patent_app_type] => utility
[patent_app_number] => 17/336877
[patent_app_country] => US
[patent_app_date] => 2021-06-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5970
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336877
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/336877 | SYSTEMS AND METHODS FOR SUPPORTING INTER-CHASSIS MANAGEABILITY OF NVME OVER FABRICS BASED SYSTEMS | Jun 1, 2021 | Abandoned |
Array
(
[id] => 18038340
[patent_doc_number] => 20220382556
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-12-01
[patent_title] => METHOD AND APPARATUS FOR A LOGIC-BASED FILTER ENGINE
[patent_app_type] => utility
[patent_app_number] => 17/331237
[patent_app_country] => US
[patent_app_date] => 2021-05-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7537
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -13
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17331237
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/331237 | METHOD AND APPARATUS FOR A LOGIC-BASED FILTER ENGINE | May 25, 2021 | Abandoned |
Array
(
[id] => 19294890
[patent_doc_number] => 12034256
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-07-09
[patent_title] => Systems, devices, and methods for connectors
[patent_app_type] => utility
[patent_app_number] => 17/329559
[patent_app_country] => US
[patent_app_date] => 2021-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 4024
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 138
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17329559
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/329559 | Systems, devices, and methods for connectors | May 24, 2021 | Issued |
Array
(
[id] => 19719367
[patent_doc_number] => 12204906
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-01-21
[patent_title] => Profiling of sampled operations processed by processing circuitry
[patent_app_type] => utility
[patent_app_number] => 17/999167
[patent_app_country] => US
[patent_app_date] => 2021-05-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 14
[patent_no_of_words] => 19135
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17999167
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/999167 | Profiling of sampled operations processed by processing circuitry | May 19, 2021 | Issued |
Array
(
[id] => 18677830
[patent_doc_number] => 20230315477
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-10-05
[patent_title] => COMPUTING APPARATUS, INTEGRATED CIRCUIT CHIP, BOARD CARD, ELECTRONIC DEVICE AND COMPUTING METHOD
[patent_app_type] => utility
[patent_app_number] => 18/013748
[patent_app_country] => US
[patent_app_date] => 2021-05-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 15946
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18013748
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/013748 | COMPUTING APPARATUS, INTEGRATED CIRCUIT CHIP, BOARD CARD, ELECTRONIC DEVICE AND COMPUTING METHOD | May 18, 2021 | Pending |
Array
(
[id] => 17431447
[patent_doc_number] => 20220059156
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-02-24
[patent_title] => METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING SELECTIVE EQUALIZATION, METHOD OF TRANSMITTING DATA USING THE SAME, AND TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/321678
[patent_app_country] => US
[patent_app_date] => 2021-05-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14812
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17321678
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/321678 | METHOD OF GENERATING A MULTI-LEVEL SIGNAL USING SELECTIVE EQUALIZATION, METHOD OF TRANSMITTING DATA USING THE SAME, AND TRANSMITTER AND MEMORY SYSTEM PERFORMING THE SAME | May 16, 2021 | Abandoned |
Array
(
[id] => 17962250
[patent_doc_number] => 20220342831
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-27
[patent_title] => VIRTUAL NETWORK STORAGE ARRAY DATA TRANSMISSIONS
[patent_app_type] => utility
[patent_app_number] => 17/236395
[patent_app_country] => US
[patent_app_date] => 2021-04-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6556
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 110
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17236395
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/236395 | VIRTUAL NETWORK STORAGE ARRAY DATA TRANSMISSIONS | Apr 20, 2021 | Abandoned |
Array
(
[id] => 17447854
[patent_doc_number] => 20220068359
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-03-03
[patent_title] => MULTI-LEVEL SIGNAL RECEIVERS AND MEMORY SYSTEMS INCLUDING THE SAME
[patent_app_type] => utility
[patent_app_number] => 17/228943
[patent_app_country] => US
[patent_app_date] => 2021-04-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13541
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17228943
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/228943 | Multi-level signal receivers and memory systems including the same | Apr 12, 2021 | Issued |
Array
(
[id] => 17114007
[patent_doc_number] => 20210294604
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-09-23
[patent_title] => APPARATUS AND METHOD FOR PERFORMING DUAL SIGNED AND UNSIGNED MULTIPLICATION OF PACKED DATA ELEMENTS
[patent_app_type] => utility
[patent_app_number] => 17/226986
[patent_app_country] => US
[patent_app_date] => 2021-04-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 17779
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -22
[patent_words_short_claim] => 86
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17226986
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/226986 | Apparatus and method for performing dual signed and unsigned multiplication of packed data elements | Apr 8, 2021 | Issued |
Array
(
[id] => 17931830
[patent_doc_number] => 20220326955
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-13
[patent_title] => DYNAMIC EVENT SECURITIZATION AND NEURAL NETWORK ANALYSIS SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/224536
[patent_app_country] => US
[patent_app_date] => 2021-04-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13356
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 251
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17224536
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/224536 | Dynamic event securitization and neural network analysis system | Apr 6, 2021 | Issued |
Array
(
[id] => 17915621
[patent_doc_number] => 20220318017
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-10-06
[patent_title] => INVARIANT STATISTICS-BASED CONFIGURATION OF PROCESSOR COMPONENTS
[patent_app_type] => utility
[patent_app_number] => 17/217101
[patent_app_country] => US
[patent_app_date] => 2021-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7321
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 38
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17217101
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/217101 | Invariant statistics-based configuration of processor components | Mar 29, 2021 | Issued |