Search

Scott E. Sonners

Examiner (ID: 1691, Phone: (571)270-7504 , Office: P/2617 )

Most Active Art Unit
2613
Art Unit(s)
2678, 2628, 2617, 4175, 2613
Total Applications
452
Issued Applications
300
Pending Applications
38
Abandoned Applications
122

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17187453 [patent_doc_number] => 20210334338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => Hardware Accelerated Discretized Neural Network [patent_app_type] => utility [patent_app_number] => 17/370716 [patent_app_country] => US [patent_app_date] => 2021-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17370716 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/370716
Hardware accelerated discretized neural network Jul 7, 2021 Issued
Array ( [id] => 17644291 [patent_doc_number] => 20220172030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => NUMERICAL REPRESENTATION FOR NEURAL NETWORKS [patent_app_type] => utility [patent_app_number] => 17/367861 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 67873 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17367861 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/367861
NUMERICAL REPRESENTATION FOR NEURAL NETWORKS Jul 5, 2021 Abandoned
Array ( [id] => 18622805 [patent_doc_number] => 11755850 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Single transistor multiplier and method therefor [patent_app_type] => utility [patent_app_number] => 17/362376 [patent_app_country] => US [patent_app_date] => 2021-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3011 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17362376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/362376
Single transistor multiplier and method therefor Jun 28, 2021 Issued
Array ( [id] => 19475975 [patent_doc_number] => 12106069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-01 [patent_title] => Power saving floating point multiplier-accumulator with precision-aware accumulation [patent_app_type] => utility [patent_app_number] => 17/352370 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 387 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352370 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352370
Power saving floating point multiplier-accumulator with precision-aware accumulation Jun 20, 2021 Issued
Array ( [id] => 19703853 [patent_doc_number] => 12197889 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-14 [patent_title] => Process for dual mode floating point multiplier-accumulator with high precision mode for near zero accumulation results [patent_app_type] => utility [patent_app_number] => 17/352374 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 7897 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 536 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17352374 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/352374
Process for dual mode floating point multiplier-accumulator with high precision mode for near zero accumulation results Jun 20, 2021 Issued
Array ( [id] => 17143721 [patent_doc_number] => 20210311734 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/351175 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21280 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351175 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351175
Generalized acceleration of matrix multiply accumulate operations Jun 16, 2021 Issued
Array ( [id] => 17143720 [patent_doc_number] => 20210311733 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/351161 [patent_app_country] => US [patent_app_date] => 2021-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 21272 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17351161 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/351161
Generalized acceleration of matrix multiply accumulate operations Jun 16, 2021 Issued
Array ( [id] => 17144001 [patent_doc_number] => 20210312014 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-07 [patent_title] => ASYMMETRIC ALLOCATION OF SRAM AND DATA LAYOUT FOR EFFICIENT MATRIX-MATRIX MULTIPLICATION [patent_app_type] => utility [patent_app_number] => 17/349817 [patent_app_country] => US [patent_app_date] => 2021-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9071 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17349817 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/349817
Asymmetric allocation of SRAM and data layout for efficient matrix-matrix multiplication Jun 15, 2021 Issued
Array ( [id] => 19811557 [patent_doc_number] => 12242951 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-04 [patent_title] => Highly parallel convolutional neural network [patent_app_type] => utility [patent_app_number] => 17/348395 [patent_app_country] => US [patent_app_date] => 2021-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 10833 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17348395 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/348395
Highly parallel convolutional neural network Jun 14, 2021 Issued
Array ( [id] => 17475810 [patent_doc_number] => 20220083314 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-03-17 [patent_title] => FLEXIBLE ACCELERATOR FOR A TENSOR WORKLOAD [patent_app_type] => utility [patent_app_number] => 17/343597 [patent_app_country] => US [patent_app_date] => 2021-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -41 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17343597 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/343597
FLEXIBLE ACCELERATOR FOR A TENSOR WORKLOAD Jun 8, 2021 Abandoned
Array ( [id] => 17278866 [patent_doc_number] => 20210385064 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => METHOD OF REAL-TIME HIGH-SPEED QUANTUM RANDOM NUMBER GENERATION BASED ON CHAOS AMPLIFYING QUANTUM NOISE [patent_app_type] => utility [patent_app_number] => 17/337689 [patent_app_country] => US [patent_app_date] => 2021-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3224 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 534 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17337689 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/337689
Method of real-time high-speed quantum random number generation based on chaos amplifying quantum noise Jun 2, 2021 Issued
Array ( [id] => 18191283 [patent_doc_number] => 11581894 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Alternative data selector, full adder and ripple carry adder [patent_app_type] => utility [patent_app_number] => 17/629153 [patent_app_country] => US [patent_app_date] => 2021-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 6993 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17629153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/629153
Alternative data selector, full adder and ripple carry adder May 23, 2021 Issued
Array ( [id] => 18022997 [patent_doc_number] => 20220374496 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-11-24 [patent_title] => TECHNIQUES FOR ACCELERATING MATRIX MULTIPLICATION COMPUTATIONS USING HIERARCHICAL REPRESENTATIONS OF SPARSE MATRICES [patent_app_type] => utility [patent_app_number] => 17/325120 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17325120 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/325120
Techniques for accelerating matrix multiplication computations using hierarchical representations of sparse matrices May 18, 2021 Issued
Array ( [id] => 17069520 [patent_doc_number] => 20210271736 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-02 [patent_title] => METHOD, CIRCUIT, AND SOC FOR PERFORMING MATRIX MULTIPLICATION OPERATION [patent_app_type] => utility [patent_app_number] => 17/324533 [patent_app_country] => US [patent_app_date] => 2021-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14928 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17324533 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/324533
Method, circuit, and SOC for performing matrix multiplication operation May 18, 2021 Issued
Array ( [id] => 17231385 [patent_doc_number] => 20210357942 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-11-18 [patent_title] => METHOD AND APPARATUS FOR IDENTIFYING RISKY VERTICES [patent_app_type] => utility [patent_app_number] => 17/323549 [patent_app_country] => US [patent_app_date] => 2021-05-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17323549 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/323549
Method and apparatus for identifying risky vertices May 17, 2021 Issued
Array ( [id] => 17832177 [patent_doc_number] => 20220269481 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => FULL ADDER, CHIP AND COMPUTING DEVICE [patent_app_type] => utility [patent_app_number] => 17/628476 [patent_app_country] => US [patent_app_date] => 2021-05-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7710 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17628476 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/628476
Full adder, chip and computing device May 13, 2021 Issued
Array ( [id] => 17054562 [patent_doc_number] => 20210263996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-08-26 [patent_title] => IDENTIFYING CHECKSUM MECHANISMS USING LINEAR EQUATIONS [patent_app_type] => utility [patent_app_number] => 17/316822 [patent_app_country] => US [patent_app_date] => 2021-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17316822 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/316822
Identifying checksum mechanisms using linear equations May 10, 2021 Issued
Array ( [id] => 17084425 [patent_doc_number] => 20210279432 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-09-09 [patent_title] => HYBRID ANALOG-DIGITAL MATRIX PROCESSORS [patent_app_type] => utility [patent_app_number] => 17/246892 [patent_app_country] => US [patent_app_date] => 2021-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 27653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17246892 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/246892
Hybrid analog-digital matrix processors May 2, 2021 Issued
Array ( [id] => 19581665 [patent_doc_number] => 12147783 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-19 [patent_title] => Pipelined hardware to accelerate modular arithmetic operations [patent_app_type] => utility [patent_app_number] => 17/242351 [patent_app_country] => US [patent_app_date] => 2021-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13142 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17242351 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/242351
Pipelined hardware to accelerate modular arithmetic operations Apr 27, 2021 Issued
Array ( [id] => 17644289 [patent_doc_number] => 20220172028 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => METHOD AND APPARATUS WITH NEURAL NETWORK OPERATION AND KEYWORD SPOTTING [patent_app_type] => utility [patent_app_number] => 17/229273 [patent_app_country] => US [patent_app_date] => 2021-04-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17229273 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/229273
Method and apparatus with neural network operation and keyword spotting Apr 12, 2021 Issued
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