
Scott Ouellette
Examiner (ID: 16636)
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2504 |
| Total Applications | 229 |
| Issued Applications | 218 |
| Pending Applications | 0 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2713894
[patent_doc_number] => 05041743
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-20
[patent_title] => 'Emitter-follower circuit with reduced delay time'
[patent_app_type] => 1
[patent_app_number] => 7/558308
[patent_app_country] => US
[patent_app_date] => 1990-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 15
[patent_no_of_words] => 4008
[patent_no_of_claims] => 5
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 165
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/041/05041743.pdf
[firstpage_image] =>[orig_patent_app_number] => 558308
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/558308 | Emitter-follower circuit with reduced delay time | Jul 24, 1990 | Issued |
Array
(
[id] => 2710949
[patent_doc_number] => 05013936
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-07
[patent_title] => 'BiCMOS logic circuit using complementary bipolar transistors having their emitters connected together'
[patent_app_type] => 1
[patent_app_number] => 7/551359
[patent_app_country] => US
[patent_app_date] => 1990-07-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 8462
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 308
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/013/05013936.pdf
[firstpage_image] =>[orig_patent_app_number] => 551359
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/551359 | BiCMOS logic circuit using complementary bipolar transistors having their emitters connected together | Jul 11, 1990 | Issued |
Array
(
[id] => 2710804
[patent_doc_number] => 05001370
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-03-19
[patent_title] => 'High speed ECL to TTL translator having a non-Schottky clamp for the output stage transistor'
[patent_app_type] => 1
[patent_app_number] => 7/547257
[patent_app_country] => US
[patent_app_date] => 1990-07-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3806
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/001/05001370.pdf
[firstpage_image] =>[orig_patent_app_number] => 547257
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/547257 | High speed ECL to TTL translator having a non-Schottky clamp for the output stage transistor | Jul 1, 1990 | Issued |
Array
(
[id] => 2777621
[patent_doc_number] => 05075567
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-24
[patent_title] => 'Electronic switch circuit'
[patent_app_type] => 1
[patent_app_number] => 7/545920
[patent_app_country] => US
[patent_app_date] => 1990-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 4
[patent_no_of_words] => 4253
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 183
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/075/05075567.pdf
[firstpage_image] =>[orig_patent_app_number] => 545920
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/545920 | Electronic switch circuit | Jun 28, 1990 | Issued |
Array
(
[id] => 2847065
[patent_doc_number] => 05138201
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Sense amplifier operable under variable power supply voltage'
[patent_app_type] => 1
[patent_app_number] => 7/542225
[patent_app_country] => US
[patent_app_date] => 1990-06-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 13
[patent_no_of_words] => 5043
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 162
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138201.pdf
[firstpage_image] =>[orig_patent_app_number] => 542225
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/542225 | Sense amplifier operable under variable power supply voltage | Jun 21, 1990 | Issued |
| 07/540334 | BUFFER CIRCUIT HAVING A VOLTAGE DROP MEANS | Jun 18, 1990 | Abandoned |
Array
(
[id] => 2686125
[patent_doc_number] => 05045734
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-03
[patent_title] => 'High power switch'
[patent_app_type] => 1
[patent_app_number] => 7/535321
[patent_app_country] => US
[patent_app_date] => 1990-06-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 2329
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 127
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/045/05045734.pdf
[firstpage_image] =>[orig_patent_app_number] => 535321
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/535321 | High power switch | Jun 7, 1990 | Issued |
Array
(
[id] => 2737525
[patent_doc_number] => 05039892
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-13
[patent_title] => 'High speed data/tri-state sense circuit'
[patent_app_type] => 1
[patent_app_number] => 7/534756
[patent_app_country] => US
[patent_app_date] => 1990-06-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 3556
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 68
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/039/05039892.pdf
[firstpage_image] =>[orig_patent_app_number] => 534756
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/534756 | High speed data/tri-state sense circuit | Jun 6, 1990 | Issued |
Array
(
[id] => 2749480
[patent_doc_number] => 05012126
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'High speed CMOS multiplexer having reduced propagation delay'
[patent_app_type] => 1
[patent_app_number] => 7/533206
[patent_app_country] => US
[patent_app_date] => 1990-06-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 3851
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 182
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012126.pdf
[firstpage_image] =>[orig_patent_app_number] => 533206
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/533206 | High speed CMOS multiplexer having reduced propagation delay | Jun 3, 1990 | Issued |
Array
(
[id] => 2749536
[patent_doc_number] => 05012129
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-04-30
[patent_title] => 'Line driver'
[patent_app_type] => 1
[patent_app_number] => 7/530884
[patent_app_country] => US
[patent_app_date] => 1990-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1897
[patent_no_of_claims] => 7
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 82
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/012/05012129.pdf
[firstpage_image] =>[orig_patent_app_number] => 530884
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530884 | Line driver | May 29, 1990 | Issued |
Array
(
[id] => 2728185
[patent_doc_number] => 05057711
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-15
[patent_title] => 'Noise reducing output buffer circuit for an integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/530819
[patent_app_country] => US
[patent_app_date] => 1990-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 3064
[patent_no_of_claims] => 4
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 289
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/057/05057711.pdf
[firstpage_image] =>[orig_patent_app_number] => 530819
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/530819 | Noise reducing output buffer circuit for an integrated circuit | May 29, 1990 | Issued |
Array
(
[id] => 2650127
[patent_doc_number] => 04980581
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1990-12-25
[patent_title] => 'Differential ECL bus tri-state detection receiver'
[patent_app_type] => 1
[patent_app_number] => 7/526267
[patent_app_country] => US
[patent_app_date] => 1990-05-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3949
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 129
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/04/980/04980581.pdf
[firstpage_image] =>[orig_patent_app_number] => 526267
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/526267 | Differential ECL bus tri-state detection receiver | May 20, 1990 | Issued |
Array
(
[id] => 2823375
[patent_doc_number] => 05081412
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-01-14
[patent_title] => 'Current conduction probe circuit'
[patent_app_type] => 1
[patent_app_number] => 7/525835
[patent_app_country] => US
[patent_app_date] => 1990-05-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 899
[patent_no_of_claims] => 2
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 150
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/081/05081412.pdf
[firstpage_image] =>[orig_patent_app_number] => 525835
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/525835 | Current conduction probe circuit | May 17, 1990 | Issued |
Array
(
[id] => 2714004
[patent_doc_number] => 05017813
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-05-21
[patent_title] => 'Input/output module with latches'
[patent_app_type] => 1
[patent_app_number] => 7/522389
[patent_app_country] => US
[patent_app_date] => 1990-05-11
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 1431
[patent_no_of_claims] => 3
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 112
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/017/05017813.pdf
[firstpage_image] =>[orig_patent_app_number] => 522389
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/522389 | Input/output module with latches | May 10, 1990 | Issued |
Array
(
[id] => 2753092
[patent_doc_number] => 05030855
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Current logic transceiver'
[patent_app_type] => 1
[patent_app_number] => 7/521268
[patent_app_country] => US
[patent_app_date] => 1990-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 2041
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 126
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/030/05030855.pdf
[firstpage_image] =>[orig_patent_app_number] => 521268
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/521268 | Current logic transceiver | May 7, 1990 | Issued |
Array
(
[id] => 2748113
[patent_doc_number] => 05023489
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-06-11
[patent_title] => 'Integrator circuit'
[patent_app_type] => 1
[patent_app_number] => 7/520696
[patent_app_country] => US
[patent_app_date] => 1990-05-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 6891
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 197
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/023/05023489.pdf
[firstpage_image] =>[orig_patent_app_number] => 520696
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/520696 | Integrator circuit | May 7, 1990 | Issued |
Array
(
[id] => 2753029
[patent_doc_number] => 05030852
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-07-09
[patent_title] => 'Quasicomplementary MESFET logic circuit with increased noise imunity'
[patent_app_type] => 1
[patent_app_number] => 7/517626
[patent_app_country] => US
[patent_app_date] => 1990-05-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 16
[patent_no_of_words] => 7144
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 7
[patent_words_short_claim] => 115
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/030/05030852.pdf
[firstpage_image] =>[orig_patent_app_number] => 517626
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/517626 | Quasicomplementary MESFET logic circuit with increased noise imunity | Apr 30, 1990 | Issued |
| 07/516752 | PRECISION TIMING CONTROL PROGRAMMABLE LOGIC DEVICE | Apr 29, 1990 | Abandoned |
Array
(
[id] => 2763408
[patent_doc_number] => 05059834
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-22
[patent_title] => 'Circuit device for eliminating noise from an input signal independent of time of arrival of noise or noise width'
[patent_app_type] => 1
[patent_app_number] => 7/512153
[patent_app_country] => US
[patent_app_date] => 1990-04-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 12
[patent_no_of_words] => 5007
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 258
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/059/05059834.pdf
[firstpage_image] =>[orig_patent_app_number] => 512153
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/512153 | Circuit device for eliminating noise from an input signal independent of time of arrival of noise or noise width | Apr 19, 1990 | Issued |
Array
(
[id] => 2757574
[patent_doc_number] => 05072136
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-10
[patent_title] => 'ECL output buffer circuit with improved compensation'
[patent_app_type] => 1
[patent_app_number] => 7/509916
[patent_app_country] => US
[patent_app_date] => 1990-04-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 4
[patent_no_of_words] => 3698
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 135
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/072/05072136.pdf
[firstpage_image] =>[orig_patent_app_number] => 509916
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/509916 | ECL output buffer circuit with improved compensation | Apr 15, 1990 | Issued |