
Scott Ouellette
Examiner (ID: 18694)
| Most Active Art Unit | 2504 |
| Art Unit(s) | 2504 |
| Total Applications | 229 |
| Issued Applications | 218 |
| Pending Applications | 0 |
| Abandoned Applications | 11 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 2956646
[patent_doc_number] => 05181231
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-19
[patent_title] => 'Non-volatile counting method and apparatus'
[patent_app_type] => 1
[patent_app_number] => 7/620499
[patent_app_country] => US
[patent_app_date] => 1990-11-30
[patent_effective_date] => 0000-00-00
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[patent_figures_cnt] => 6
[patent_no_of_words] => 4464
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[pdf_file] => patents/05/181/05181231.pdf
[firstpage_image] =>[orig_patent_app_number] => 620499
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/620499 | Non-volatile counting method and apparatus | Nov 29, 1990 | Issued |
Array
(
[id] => 2834204
[patent_doc_number] => 05128563
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-07
[patent_title] => 'CMOS bootstrapped output driver method and circuit'
[patent_app_type] => 1
[patent_app_number] => 7/619164
[patent_app_country] => US
[patent_app_date] => 1990-11-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/128/05128563.pdf
[firstpage_image] =>[orig_patent_app_number] => 619164
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/619164 | CMOS bootstrapped output driver method and circuit | Nov 27, 1990 | Issued |
Array
(
[id] => 2739719
[patent_doc_number] => 05077493
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-12-31
[patent_title] => 'Wired logic circuit for use in gate array integrated circuit'
[patent_app_type] => 1
[patent_app_number] => 7/618841
[patent_app_country] => US
[patent_app_date] => 1990-11-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/077/05077493.pdf
[firstpage_image] =>[orig_patent_app_number] => 618841
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/618841 | Wired logic circuit for use in gate array integrated circuit | Nov 27, 1990 | Issued |
Array
(
[id] => 2798897
[patent_doc_number] => 05144159
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-09-01
[patent_title] => 'Power-on-reset (POR) circuit having power supply rise time independence'
[patent_app_type] => 1
[patent_app_number] => 7/617713
[patent_app_country] => US
[patent_app_date] => 1990-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[pdf_file] => patents/05/144/05144159.pdf
[firstpage_image] =>[orig_patent_app_number] => 617713
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/617713 | Power-on-reset (POR) circuit having power supply rise time independence | Nov 25, 1990 | Issued |
Array
(
[id] => 2790132
[patent_doc_number] => 05130573
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-07-14
[patent_title] => 'Semiconductor integrated circuit having ECL circuits and a circuit for compensating a capacitive load'
[patent_app_type] => 1
[patent_app_number] => 7/616947
[patent_app_country] => US
[patent_app_date] => 1990-11-21
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[pdf_file] => patents/05/130/05130573.pdf
[firstpage_image] =>[orig_patent_app_number] => 616947
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/616947 | Semiconductor integrated circuit having ECL circuits and a circuit for compensating a capacitive load | Nov 20, 1990 | Issued |
Array
(
[id] => 2803433
[patent_doc_number] => 05140184
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-18
[patent_title] => 'Clock feeding circuit and clock wiring system'
[patent_app_type] => 1
[patent_app_number] => 7/615930
[patent_app_country] => US
[patent_app_date] => 1990-11-20
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/140/05140184.pdf
[firstpage_image] =>[orig_patent_app_number] => 615930
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/615930 | Clock feeding circuit and clock wiring system | Nov 19, 1990 | Issued |
Array
(
[id] => 2795236
[patent_doc_number] => 05103118
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-04-07
[patent_title] => 'High speed anti-undershoot and anti-overshoot circuit'
[patent_app_type] => 1
[patent_app_number] => 7/615077
[patent_app_country] => US
[patent_app_date] => 1990-11-19
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/103/05103118.pdf
[firstpage_image] =>[orig_patent_app_number] => 615077
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/615077 | High speed anti-undershoot and anti-overshoot circuit | Nov 18, 1990 | Issued |
Array
(
[id] => 2768965
[patent_doc_number] => 05063310
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-11-05
[patent_title] => 'Transistor write current switching circuit for magnetic recording'
[patent_app_type] => 1
[patent_app_number] => 7/614510
[patent_app_country] => US
[patent_app_date] => 1990-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
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[patent_no_of_words] => 3761
[patent_no_of_claims] => 17
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/063/05063310.pdf
[firstpage_image] =>[orig_patent_app_number] => 614510
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/614510 | Transistor write current switching circuit for magnetic recording | Nov 15, 1990 | Issued |
Array
(
[id] => 2856772
[patent_doc_number] => 05126601
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-30
[patent_title] => 'Driver and receiver for a differential-signal electrical interface'
[patent_app_type] => 1
[patent_app_number] => 7/613181
[patent_app_country] => US
[patent_app_date] => 1990-11-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/05/126/05126601.pdf
[firstpage_image] =>[orig_patent_app_number] => 613181
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/613181 | Driver and receiver for a differential-signal electrical interface | Nov 14, 1990 | Issued |
Array
(
[id] => 2846917
[patent_doc_number] => 05138194
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-08-11
[patent_title] => 'Controlled slew rate buffer'
[patent_app_type] => 1
[patent_app_number] => 7/610852
[patent_app_country] => US
[patent_app_date] => 1990-11-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2634
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/138/05138194.pdf
[firstpage_image] =>[orig_patent_app_number] => 610852
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/610852 | Controlled slew rate buffer | Nov 7, 1990 | Issued |
Array
(
[id] => 2752894
[patent_doc_number] => 05038058
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-08-06
[patent_title] => 'BiCMOS TTL output driver'
[patent_app_type] => 1
[patent_app_number] => 7/609560
[patent_app_country] => US
[patent_app_date] => 1990-11-06
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/05/038/05038058.pdf
[firstpage_image] =>[orig_patent_app_number] => 609560
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609560 | BiCMOS TTL output driver | Nov 5, 1990 | Issued |
Array
(
[id] => 2691325
[patent_doc_number] => 05049760
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-09-17
[patent_title] => 'High speed complementary flipflop'
[patent_app_type] => 1
[patent_app_number] => 7/609538
[patent_app_country] => US
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[pdf_file] => patents/05/049/05049760.pdf
[firstpage_image] =>[orig_patent_app_number] => 609538
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/609538 | High speed complementary flipflop | Nov 5, 1990 | Issued |
Array
(
[id] => 2920489
[patent_doc_number] => 05179299
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'CMOS low output voltage bus driver'
[patent_app_type] => 1
[patent_app_number] => 7/608788
[patent_app_country] => US
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[pdf_file] => patents/05/179/05179299.pdf
[firstpage_image] =>[orig_patent_app_number] => 608788
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/608788 | CMOS low output voltage bus driver | Nov 4, 1990 | Issued |
Array
(
[id] => 2810471
[patent_doc_number] => 05157278
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-10-20
[patent_title] => 'Substrate voltage generator for semiconductor device'
[patent_app_type] => 1
[patent_app_number] => 7/606031
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[pdf_file] => patents/05/157/05157278.pdf
[firstpage_image] =>[orig_patent_app_number] => 606031
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/606031 | Substrate voltage generator for semiconductor device | Oct 29, 1990 | Issued |
Array
(
[id] => 2806572
[patent_doc_number] => 05124582
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Bi-CMOS circuit with high-speed active pull-down output currents'
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[pdf_file] => patents/05/124/05124582.pdf
[firstpage_image] =>[orig_patent_app_number] => 605325
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/605325 | Bi-CMOS circuit with high-speed active pull-down output currents | Oct 29, 1990 | Issued |
Array
(
[id] => 2920453
[patent_doc_number] => 05179297
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1993-01-12
[patent_title] => 'CMOS self-adjusting bias generator for high voltage drivers'
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[pdf_file] => patents/05/179/05179297.pdf
[firstpage_image] =>[orig_patent_app_number] => 601892
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601892 | CMOS self-adjusting bias generator for high voltage drivers | Oct 21, 1990 | Issued |
Array
(
[id] => 2806424
[patent_doc_number] => 05124574
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1992-06-23
[patent_title] => 'Semiconductor device for generating a voltage higher than power source potential or lower than grounding potential'
[patent_app_type] => 1
[patent_app_number] => 7/602407
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[pdf_file] => patents/05/124/05124574.pdf
[firstpage_image] =>[orig_patent_app_number] => 602407
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/602407 | Semiconductor device for generating a voltage higher than power source potential or lower than grounding potential | Oct 21, 1990 | Issued |
Array
(
[id] => 2763204
[patent_doc_number] => 05059823
[patent_country] => US
[patent_kind] => NA
[patent_issue_date] => 1991-10-22
[patent_title] => 'Supply bounce controlled output buffer circuit'
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[pdf_file] => patents/05/059/05059823.pdf
[firstpage_image] =>[orig_patent_app_number] => 600948
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/600948 | Supply bounce controlled output buffer circuit | Oct 21, 1990 | Issued |
Array
(
[id] => 2828358
[patent_doc_number] => 05170078
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[patent_title] => 'Highly stable high-voltage output buffer using CMOS technology'
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[pdf_file] => patents/05/170/05170078.pdf
[firstpage_image] =>[orig_patent_app_number] => 601282
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601282 | Highly stable high-voltage output buffer using CMOS technology | Oct 21, 1990 | Issued |
Array
(
[id] => 2834703
[patent_doc_number] => 05099148
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[patent_kind] => NA
[patent_issue_date] => 1992-03-24
[patent_title] => 'Integrated circuit having multiple data outputs sharing a resistor network'
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[pdf_file] => patents/05/099/05099148.pdf
[firstpage_image] =>[orig_patent_app_number] => 601288
[rel_patent_id] =>[rel_patent_doc_number] =>) 07/601288 | Integrated circuit having multiple data outputs sharing a resistor network | Oct 21, 1990 | Issued |