
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 833440
[patent_doc_number] => 07396729
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2008-07-08
[patent_title] => 'Methods of forming semiconductor devices having a trench with beveled corners'
[patent_app_type] => utility
[patent_app_number] => 11/216661
[patent_app_country] => US
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[pdf_file] => patents/07/396/07396729.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/216661 | Methods of forming semiconductor devices having a trench with beveled corners | Aug 30, 2005 | Issued |
Array
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[patent_doc_number] => 08110469
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[patent_kind] => B2
[patent_issue_date] => 2012-02-07
[patent_title] => 'Graded dielectric layers'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/216542 | Graded dielectric layers | Aug 29, 2005 | Issued |
Array
(
[id] => 4932922
[patent_doc_number] => 20080003697
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'INTEGRATION PROCESSES FOR FABRICATING A CONDUCTIVE METAL OXIDE GATE FERROELECTRIC MEMORY TRANSISTOR'
[patent_app_type] => utility
[patent_app_number] => 11/215521
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[patent_app_date] => 2005-08-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/215521 | Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor | Aug 29, 2005 | Issued |
Array
(
[id] => 5337439
[patent_doc_number] => 20090053903
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-02-26
[patent_title] => 'SILICON OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND COMPUTER STORAGE MEDIUM'
[patent_app_type] => utility
[patent_app_number] => 11/574422
[patent_app_country] => US
[patent_app_date] => 2005-08-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/574422 | SILICON OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND COMPUTER STORAGE MEDIUM | Aug 29, 2005 | Abandoned |
Array
(
[id] => 5903538
[patent_doc_number] => 20060046427
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[patent_kind] => A1
[patent_issue_date] => 2006-03-02
[patent_title] => 'Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials'
[patent_app_type] => utility
[patent_app_number] => 11/213612
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/213612 | Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials | Aug 25, 2005 | Issued |
Array
(
[id] => 817007
[patent_doc_number] => 07410815
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[patent_issue_date] => 2008-08-12
[patent_title] => 'Apparatus and method for non-contact assessment of a constituent in semiconductor substrates'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/212971 | Apparatus and method for non-contact assessment of a constituent in semiconductor substrates | Aug 24, 2005 | Issued |
Array
(
[id] => 397613
[patent_doc_number] => 07294582
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-13
[patent_title] => 'Low temperature silicon compound deposition'
[patent_app_type] => utility
[patent_app_number] => 11/213449
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/213449 | Low temperature silicon compound deposition | Aug 24, 2005 | Issued |
Array
(
[id] => 6929042
[patent_doc_number] => 20050280075
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[patent_issue_date] => 2005-12-22
[patent_title] => 'Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor'
[patent_app_type] => utility
[patent_app_number] => 11/209881
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Array
(
[id] => 5895005
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[patent_title] => 'Methods of forming trench isolation regions'
[patent_app_type] => utility
[patent_app_number] => 11/209081
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[firstpage_image] =>[orig_patent_app_number] => 11209081
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/209081 | Methods of forming trench isolation regions with nitride liner | Aug 21, 2005 | Issued |
Array
(
[id] => 356211
[patent_doc_number] => 07488647
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[patent_issue_date] => 2009-02-10
[patent_title] => 'System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird\'s beak structure in the manufacture of a semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 11/201761
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Array
(
[id] => 5760281
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[patent_title] => 'Partial implantation method for semiconductor manufacturing'
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Array
(
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[patent_title] => 'Suppression of cross diffusion and gate depletion'
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Array
(
[id] => 902987
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/178612 | Semiconductor device and manufacturing method thereof with rounded gate including a silicide on the top and at the corners | Jul 11, 2005 | Issued |
Array
(
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Array
(
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