Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 833440 [patent_doc_number] => 07396729 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-07-08 [patent_title] => 'Methods of forming semiconductor devices having a trench with beveled corners' [patent_app_type] => utility [patent_app_number] => 11/216661 [patent_app_country] => US [patent_app_date] => 2005-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3645 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/396/07396729.pdf [firstpage_image] =>[orig_patent_app_number] => 11216661 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216661
Methods of forming semiconductor devices having a trench with beveled corners Aug 30, 2005 Issued
Array ( [id] => 7751455 [patent_doc_number] => 08110469 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Graded dielectric layers' [patent_app_type] => utility [patent_app_number] => 11/216542 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 8194 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 134 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110469.pdf [firstpage_image] =>[orig_patent_app_number] => 11216542 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/216542
Graded dielectric layers Aug 29, 2005 Issued
Array ( [id] => 4932922 [patent_doc_number] => 20080003697 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-01-03 [patent_title] => 'INTEGRATION PROCESSES FOR FABRICATING A CONDUCTIVE METAL OXIDE GATE FERROELECTRIC MEMORY TRANSISTOR' [patent_app_type] => utility [patent_app_number] => 11/215521 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2861 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20080003697.pdf [firstpage_image] =>[orig_patent_app_number] => 11215521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/215521
Integration processes for fabricating a conductive metal oxide gate ferroelectric memory transistor Aug 29, 2005 Issued
Array ( [id] => 5337439 [patent_doc_number] => 20090053903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-02-26 [patent_title] => 'SILICON OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND COMPUTER STORAGE MEDIUM' [patent_app_type] => utility [patent_app_number] => 11/574422 [patent_app_country] => US [patent_app_date] => 2005-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 9730 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20090053903.pdf [firstpage_image] =>[orig_patent_app_number] => 11574422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/574422
SILICON OXIDE FILM FORMING METHOD, SEMICONDUCTOR DEVICE MANUFACTURING METHOD AND COMPUTER STORAGE MEDIUM Aug 29, 2005 Abandoned
Array ( [id] => 5903538 [patent_doc_number] => 20060046427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials' [patent_app_type] => utility [patent_app_number] => 11/213612 [patent_app_country] => US [patent_app_date] => 2005-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 7740 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046427.pdf [firstpage_image] =>[orig_patent_app_number] => 11213612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213612
Gap-fill depositions introducing hydroxyl-containing precursors in the formation of silicon containing dielectric materials Aug 25, 2005 Issued
Array ( [id] => 817007 [patent_doc_number] => 07410815 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-08-12 [patent_title] => 'Apparatus and method for non-contact assessment of a constituent in semiconductor substrates' [patent_app_type] => utility [patent_app_number] => 11/212971 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3673 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 50 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/410/07410815.pdf [firstpage_image] =>[orig_patent_app_number] => 11212971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/212971
Apparatus and method for non-contact assessment of a constituent in semiconductor substrates Aug 24, 2005 Issued
Array ( [id] => 397613 [patent_doc_number] => 07294582 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Low temperature silicon compound deposition' [patent_app_type] => utility [patent_app_number] => 11/213449 [patent_app_country] => US [patent_app_date] => 2005-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 12258 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294582.pdf [firstpage_image] =>[orig_patent_app_number] => 11213449 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/213449
Low temperature silicon compound deposition Aug 24, 2005 Issued
Array ( [id] => 6929042 [patent_doc_number] => 20050280075 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-22 [patent_title] => 'Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor' [patent_app_type] => utility [patent_app_number] => 11/209881 [patent_app_country] => US [patent_app_date] => 2005-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 103 [patent_figures_cnt] => 103 [patent_no_of_words] => 45263 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11209881 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209881
Semiconductor integrated circuit device having improved punch-through resistance and production method thereof, semiconductor integrated circuit device including a low-voltage transistor and a high-voltage transistor Aug 23, 2005 Issued
Array ( [id] => 5895005 [patent_doc_number] => 20060003544 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-05 [patent_title] => 'Methods of forming trench isolation regions' [patent_app_type] => utility [patent_app_number] => 11/209081 [patent_app_country] => US [patent_app_date] => 2005-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3538 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20060003544.pdf [firstpage_image] =>[orig_patent_app_number] => 11209081 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/209081
Methods of forming trench isolation regions with nitride liner Aug 21, 2005 Issued
Array ( [id] => 356211 [patent_doc_number] => 07488647 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-02-10 [patent_title] => 'System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird\'s beak structure in the manufacture of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/201761 [patent_app_country] => US [patent_app_date] => 2005-08-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2138 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488647.pdf [firstpage_image] =>[orig_patent_app_number] => 11201761 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/201761
System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device Aug 10, 2005 Issued
Array ( [id] => 5760281 [patent_doc_number] => 20060211226 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-21 [patent_title] => 'Partial implantation method for semiconductor manufacturing' [patent_app_type] => utility [patent_app_number] => 11/197091 [patent_app_country] => US [patent_app_date] => 2005-08-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 8823 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0211/20060211226.pdf [firstpage_image] =>[orig_patent_app_number] => 11197091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/197091
Partial implantation method for semiconductor manufacturing Aug 3, 2005 Issued
Array ( [id] => 5771124 [patent_doc_number] => 20050266666 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Suppression of cross diffusion and gate depletion' [patent_app_type] => utility [patent_app_number] => 11/191512 [patent_app_country] => US [patent_app_date] => 2005-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5483 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20050266666.pdf [firstpage_image] =>[orig_patent_app_number] => 11191512 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/191512
Suppression of cross diffusion and gate depletion Jul 27, 2005 Abandoned
Array ( [id] => 902987 [patent_doc_number] => 07335564 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Method for forming device isolation layer of semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/182252 [patent_app_country] => US [patent_app_date] => 2005-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 2232 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/335/07335564.pdf [firstpage_image] =>[orig_patent_app_number] => 11182252 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/182252
Method for forming device isolation layer of semiconductor device Jul 13, 2005 Issued
Array ( [id] => 356234 [patent_doc_number] => 07488670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-10 [patent_title] => 'Direct channel stress' [patent_app_type] => utility [patent_app_number] => 11/180432 [patent_app_country] => US [patent_app_date] => 2005-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 4374 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/488/07488670.pdf [firstpage_image] =>[orig_patent_app_number] => 11180432 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/180432
Direct channel stress Jul 12, 2005 Issued
Array ( [id] => 5736088 [patent_doc_number] => 20060006478 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-01-12 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 11/178612 [patent_app_country] => US [patent_app_date] => 2005-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 16990 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20060006478.pdf [firstpage_image] =>[orig_patent_app_number] => 11178612 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/178612
Semiconductor device and manufacturing method thereof with rounded gate including a silicide on the top and at the corners Jul 11, 2005 Issued
Array ( [id] => 5810887 [patent_doc_number] => 20060081995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Soldered material, semiconductor device, method of soldering, and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/176422 [patent_app_country] => US [patent_app_date] => 2005-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8568 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0081/20060081995.pdf [firstpage_image] =>[orig_patent_app_number] => 11176422 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/176422
Soldered material, semiconductor device, method of soldering, and method of manufacturing semiconductor device Jul 7, 2005 Abandoned
Array ( [id] => 6926011 [patent_doc_number] => 20050239266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Method of forming trench isolation regions' [patent_app_type] => utility [patent_app_number] => 11/170522 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3338 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20050239266.pdf [firstpage_image] =>[orig_patent_app_number] => 11170522 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170522
Method of forming trench isolation regions Jun 28, 2005 Abandoned
Array ( [id] => 6926010 [patent_doc_number] => 20050239265 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'Method of forming trench isolation regions' [patent_app_type] => utility [patent_app_number] => 11/170452 [patent_app_country] => US [patent_app_date] => 2005-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3339 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20050239265.pdf [firstpage_image] =>[orig_patent_app_number] => 11170452 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/170452
Method of forming trench isolation regions Jun 28, 2005 Abandoned
Array ( [id] => 5602410 [patent_doc_number] => 20060292755 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Tunable antifuse element and method of manufacture' [patent_app_type] => utility [patent_app_number] => 11/169962 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5099 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292755.pdf [firstpage_image] =>[orig_patent_app_number] => 11169962 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/169962
Tunable antifuse element and method of manufacture Jun 27, 2005 Issued
Array ( [id] => 5602442 [patent_doc_number] => 20060292787 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-28 [patent_title] => 'Semiconductor processing methods, and semiconductor constructions' [patent_app_type] => utility [patent_app_number] => 11/168861 [patent_app_country] => US [patent_app_date] => 2005-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4936 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0292/20060292787.pdf [firstpage_image] =>[orig_patent_app_number] => 11168861 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/168861
Semiconductor processing methods Jun 27, 2005 Issued
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