
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 757845
[patent_doc_number] => 07015151
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-03-21
[patent_title] => 'Transistor fabrication methods comprising selective wet oxidation'
[patent_app_type] => utility
[patent_app_number] => 11/089714
[patent_app_country] => US
[patent_app_date] => 2005-03-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 3319
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 9
[patent_words_short_claim] => 65
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/015/07015151.pdf
[firstpage_image] =>[orig_patent_app_number] => 11089714
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/089714 | Transistor fabrication methods comprising selective wet oxidation | Mar 23, 2005 | Issued |
Array
(
[id] => 7019560
[patent_doc_number] => 20050221579
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-10-06
[patent_title] => 'Semiconductor device and method of fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/085112
[patent_app_country] => US
[patent_app_date] => 2005-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 3762
[patent_no_of_claims] => 6
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[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0221/20050221579.pdf
[firstpage_image] =>[orig_patent_app_number] => 11085112
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/085112 | Semiconductor device and method of fabricating the same | Mar 21, 2005 | Abandoned |
Array
(
[id] => 4930469
[patent_doc_number] => 20080001244
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2008-01-03
[patent_title] => 'System Comprising an Electrical Component and an Electrical Connecting Lead for Said Component, and Method for the Production of Said System'
[patent_app_type] => utility
[patent_app_number] => 10/590901
[patent_app_country] => US
[patent_app_date] => 2005-01-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
[patent_figures_cnt] => 4
[patent_no_of_words] => 5490
[patent_no_of_claims] => 30
[patent_no_of_ind_claims] => 3
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[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0001/20080001244.pdf
[firstpage_image] =>[orig_patent_app_number] => 10590901
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/590901 | System Comprising an Electrical Component and an Electrical Connecting Lead for Said Component, and Method for the Production of Said System | Jan 18, 2005 | Abandoned |
Array
(
[id] => 307329
[patent_doc_number] => 07531395
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-05-12
[patent_title] => 'Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors'
[patent_app_type] => utility
[patent_app_number] => 11/035298
[patent_app_country] => US
[patent_app_date] => 2005-01-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 11
[patent_no_of_words] => 4648
[patent_no_of_claims] => 53
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 119
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/531/07531395.pdf
[firstpage_image] =>[orig_patent_app_number] => 11035298
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/035298 | Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors | Jan 11, 2005 | Issued |
Array
(
[id] => 7178795
[patent_doc_number] => 20050124125
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-06-09
[patent_title] => 'Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors'
[patent_app_type] => utility
[patent_app_number] => 11/028755
[patent_app_country] => US
[patent_app_date] => 2005-01-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3397
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0124/20050124125.pdf
[firstpage_image] =>[orig_patent_app_number] => 11028755
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/028755 | Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors | Jan 3, 2005 | Abandoned |
Array
(
[id] => 5708093
[patent_doc_number] => 20060049437
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-03-09
[patent_title] => 'CMOS image sensors and methods for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/026182
[patent_app_country] => US
[patent_app_date] => 2004-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 3290
[patent_no_of_claims] => 12
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[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0049/20060049437.pdf
[firstpage_image] =>[orig_patent_app_number] => 11026182
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/026182 | CMOS image sensors and methods for fabricating the same | Dec 28, 2004 | Abandoned |
Array
(
[id] => 6983459
[patent_doc_number] => 20050153529
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-14
[patent_title] => 'Semiconductor devices and methods for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 11/027362
[patent_app_country] => US
[patent_app_date] => 2004-12-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 2747
[patent_no_of_claims] => 6
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0153/20050153529.pdf
[firstpage_image] =>[orig_patent_app_number] => 11027362
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/027362 | Semiconductor devices and methods for fabricating the same including forming an amorphous region in an interface between a device isolation layer and a source/drain diffusion layer | Dec 28, 2004 | Issued |
Array
(
[id] => 4441726
[patent_doc_number] => 07927907
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-19
[patent_title] => 'Method of making silicon solar cells containing μC silicon layers'
[patent_app_type] => utility
[patent_app_number] => 10/587131
[patent_app_country] => US
[patent_app_date] => 2004-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 1952
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 187
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/927/07927907.pdf
[firstpage_image] =>[orig_patent_app_number] => 10587131
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/587131 | Method of making silicon solar cells containing μC silicon layers | Dec 15, 2004 | Issued |
Array
(
[id] => 6918260
[patent_doc_number] => 20050095821
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Method of forming a polycrystalline silicon layer'
[patent_app_type] => utility
[patent_app_number] => 11/002416
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2956
[patent_no_of_claims] => 6
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0095/20050095821.pdf
[firstpage_image] =>[orig_patent_app_number] => 11002416
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/002416 | Method of forming a polycrystalline silicon layer | Dec 2, 2004 | Issued |
Array
(
[id] => 6918262
[patent_doc_number] => 20050095823
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-05
[patent_title] => 'Method of forming a polycrystalline silicon layer'
[patent_app_type] => utility
[patent_app_number] => 11/002274
[patent_app_country] => US
[patent_app_date] => 2004-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2957
[patent_no_of_claims] => 6
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[pdf_file] => publications/A1/0095/20050095823.pdf
[firstpage_image] =>[orig_patent_app_number] => 11002274
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/002274 | Method of forming a polycrystalline silicon layer | Dec 2, 2004 | Issued |
Array
(
[id] => 6936535
[patent_doc_number] => 20050110096
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-26
[patent_title] => 'CMOS TRANSISTOR WITH A POLYSILICON GATE ELECTRODE HAVING VARYING GRAIN SIZE'
[patent_app_type] => utility
[patent_app_number] => 10/904565
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
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[patent_no_of_words] => 2409
[patent_no_of_claims] => 4
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0110/20050110096.pdf
[firstpage_image] =>[orig_patent_app_number] => 10904565
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/904565 | CMOS transistor with a polysilicon gate electrode having varying grain size | Nov 15, 2004 | Issued |
Array
(
[id] => 672106
[patent_doc_number] => 07091118
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2006-08-15
[patent_title] => 'Replacement metal gate transistor with metal-rich silicon layer and method for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/988532
[patent_app_country] => US
[patent_app_date] => 2004-11-16
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/091/07091118.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988532
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988532 | Replacement metal gate transistor with metal-rich silicon layer and method for making the same | Nov 15, 2004 | Issued |
Array
(
[id] => 5892503
[patent_doc_number] => 20060001040
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-01-05
[patent_title] => 'High integrity protective coatings'
[patent_app_type] => utility
[patent_app_number] => 10/988481
[patent_app_country] => US
[patent_app_date] => 2004-11-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0001/20060001040.pdf
[firstpage_image] =>[orig_patent_app_number] => 10988481
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/988481 | High integrity protective coatings | Nov 14, 2004 | Issued |
Array
(
[id] => 6905667
[patent_doc_number] => 20050101062
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-12
[patent_title] => 'Thin film transistor array panel and manufacturing method thereof'
[patent_app_type] => utility
[patent_app_number] => 10/986672
[patent_app_country] => US
[patent_app_date] => 2004-11-12
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0101/20050101062.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986672
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986672 | Thin film transistor array panel and manufacturing method thereof | Nov 11, 2004 | Issued |
Array
(
[id] => 7156965
[patent_doc_number] => 20050083760
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics'
[patent_app_type] => utility
[patent_app_number] => 10/986615
[patent_app_country] => US
[patent_app_date] => 2004-11-12
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[pdf_file] => publications/A1/0083/20050083760.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986615
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986615 | Magnetoresistive random access memory (MRAM) cell having a diode with asymmetrical characteristics | Nov 11, 2004 | Abandoned |
Array
(
[id] => 5776890
[patent_doc_number] => 20060105530
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-18
[patent_title] => 'Method for fabricating semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/986692
[patent_app_country] => US
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[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0105/20060105530.pdf
[firstpage_image] =>[orig_patent_app_number] => 10986692
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/986692 | Method for fabricating semiconductor device | Nov 11, 2004 | Abandoned |
Array
(
[id] => 415197
[patent_doc_number] => 07279380
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-10-09
[patent_title] => 'Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method'
[patent_app_type] => utility
[patent_app_number] => 10/985481
[patent_app_country] => US
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[pdf_file] => patents/07/279/07279380.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/985481 | Method of forming a chalcogenide memory cell having an ultrasmall cross-sectional area and a chalcogenide memory cell produced by the method | Nov 9, 2004 | Issued |
Array
(
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[patent_issue_date] => 2005-06-09
[patent_title] => 'Substrate processing apparatus, control method for the apparatus, and program for implementing the method'
[patent_app_type] => utility
[patent_app_number] => 10/984982
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984982 | Substrate processing apparatus, control method for the apparatus, and program for implementing the method | Nov 9, 2004 | Issued |
Array
(
[id] => 5865669
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[patent_issue_date] => 2006-05-11
[patent_title] => 'Method for fabricating low leakage interconnect layers in integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/984701
[patent_app_country] => US
[patent_app_date] => 2004-11-09
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[firstpage_image] =>[orig_patent_app_number] => 10984701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/984701 | Method for fabricating low leakage interconnect layers in integrated circuits | Nov 8, 2004 | Abandoned |
Array
(
[id] => 5865603
[patent_doc_number] => 20060099733
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2006-05-11
[patent_title] => 'Semiconductor package and fabrication method'
[patent_app_type] => utility
[patent_app_number] => 10/985312
[patent_app_country] => US
[patent_app_date] => 2004-11-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[firstpage_image] =>[orig_patent_app_number] => 10985312
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/985312 | Semiconductor package and fabrication method | Nov 8, 2004 | Abandoned |