Scott R. Wilson

Array ( [id] => 6918174 [patent_doc_number] => 20050095735 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Electrooptic device, electronic apparatus, and method for making the electrooptic device' [patent_app_type] => utility [patent_app_number] => 10/979144 [patent_app_country] => US [patent_app_date] => 2004-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 10730 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095735.pdf [firstpage_image] =>[orig_patent_app_number] => 10979144 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7178665 [patent_doc_number] => 20050124086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-09 [patent_title] => 'Method for manufacturing a semiconductor device, and method for manufacturing a wafer' [patent_app_type] => utility [patent_app_number] => 10/975391 [patent_app_country] => US [patent_app_date] => 2004-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6738 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20050124086.pdf [firstpage_image] =>[orig_patent_app_number] => 10975391 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6926031 [patent_doc_number] => 20050239286 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-10-27 [patent_title] => 'TWO-STEP STRIPPING METHOD FOR REMOVING VIA PHOTORESIST DURING THE FABRICATION OF PARTIAL-VIA DUAL DAMASCENE FEATURES' [patent_app_type] => utility [patent_app_number] => 10/904151 [patent_app_country] => US [patent_app_date] => 2004-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1790 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20050239286.pdf [firstpage_image] =>[orig_patent_app_number] => 10904151 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4676357 [patent_doc_number] => 20080213987 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-09-04 [patent_title] => 'Method of Fabricating a Sige Semiconductor Structure' [patent_app_type] => utility [patent_app_number] => 10/587661 [patent_app_country] => US [patent_app_date] => 2004-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3863 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0213/20080213987.pdf [firstpage_image] =>[orig_patent_app_number] => 10587661 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7203830 [patent_doc_number] => 20050042822 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-24 [patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 10/950595 [patent_app_country] => US [patent_app_date] => 2004-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 50 [patent_figures_cnt] => 50 [patent_no_of_words] => 10834 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20050042822.pdf [firstpage_image] =>[orig_patent_app_number] => 10950595 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 220922 [patent_doc_number] => 07608468 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-27 [patent_title] => 'Apparatus and methods for determining overlay and uses of same' [patent_app_type] => utility [patent_app_number] => 10/950172 [patent_app_country] => US [patent_app_date] => 2004-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13833 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/608/07608468.pdf [firstpage_image] =>[orig_patent_app_number] => 10950172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 186062 [patent_doc_number] => 07646095 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-01-12 [patent_title] => 'Semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/946372 [patent_app_country] => US [patent_app_date] => 2004-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 10133 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/646/07646095.pdf [firstpage_image] =>[orig_patent_app_number] => 10946372 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 397562 [patent_doc_number] => 07294531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-13 [patent_title] => 'Wafer level chip stack method' [patent_app_type] => utility [patent_app_number] => 10/944002 [patent_app_country] => US [patent_app_date] => 2004-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 13 [patent_no_of_words] => 3644 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/294/07294531.pdf [firstpage_image] =>[orig_patent_app_number] => 10944002 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7161912 [patent_doc_number] => 20050085024 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-21 [patent_title] => 'Method for producing a field-effect transistor and transistor thus obtained' [patent_app_type] => utility [patent_app_number] => 10/943242 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4213 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20050085024.pdf [firstpage_image] =>[orig_patent_app_number] => 10943242 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7031083 [patent_doc_number] => 20050029657 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Enhanced die-up ball grid array and method for making the same' [patent_app_type] => utility [patent_app_number] => 10/942031 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11662 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20050029657.pdf [firstpage_image] =>[orig_patent_app_number] => 10942031 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7220361 [patent_doc_number] => 20050077570 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-04-14 [patent_title] => 'MIS semiconductor device and method of fabricating the same' [patent_app_type] => utility [patent_app_number] => 10/942032 [patent_app_country] => US [patent_app_date] => 2004-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 19654 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20050077570.pdf [firstpage_image] =>[orig_patent_app_number] => 10942032 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6918279 [patent_doc_number] => 20050095840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Repairing damage to low-k dielectric materials using silylating agents' [patent_app_type] => utility [patent_app_number] => 10/940682 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10842 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095840.pdf [firstpage_image] =>[orig_patent_app_number] => 10940682 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 514442 [patent_doc_number] => 07192789 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-20 [patent_title] => 'Method for monitoring an ion implanter' [patent_app_type] => utility [patent_app_number] => 10/942381 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 2419 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/192/07192789.pdf [firstpage_image] =>[orig_patent_app_number] => 10942381 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6939338 [patent_doc_number] => 20050112901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-26 [patent_title] => 'Removal of transition metal ternary and/or quaternary barrier materials from a substrate' [patent_app_type] => utility [patent_app_number] => 10/942301 [patent_app_country] => US [patent_app_date] => 2004-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5902 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0112/20050112901.pdf [firstpage_image] =>[orig_patent_app_number] => 10942301 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7010964 [patent_doc_number] => 20050064680 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-24 [patent_title] => 'Device and method for bonding wafers' [patent_app_type] => utility [patent_app_number] => 10/938931 [patent_app_country] => US [patent_app_date] => 2004-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1804 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20050064680.pdf [firstpage_image] =>[orig_patent_app_number] => 10938931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7030772 [patent_doc_number] => 20050029510 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-02-10 [patent_title] => 'Method for making electronic device comprising active optical devices with an energy band engineered superlattice' [patent_app_type] => utility [patent_app_number] => 10/937072 [patent_app_country] => US [patent_app_date] => 2004-09-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6864 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20050029510.pdf [firstpage_image] =>[orig_patent_app_number] => 10937072 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7212707 [patent_doc_number] => 20050054163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-03-10 [patent_title] => 'Method of manufacturing transistor having recessed channel' [patent_app_type] => utility [patent_app_number] => 10/937532 [patent_app_country] => US [patent_app_date] => 2004-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5658 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20050054163.pdf [firstpage_image] =>[orig_patent_app_number] => 10937532 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5903405 [patent_doc_number] => 20060046354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-03-02 [patent_title] => 'Recessed gate dielectric antifuse' [patent_app_type] => utility [patent_app_number] => 10/933161 [patent_app_country] => US [patent_app_date] => 2004-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4249 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0046/20060046354.pdf [firstpage_image] =>[orig_patent_app_number] => 10933161 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 588635 [patent_doc_number] => 07442976 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-28 [patent_title] => 'DRAM cells with vertical transistors' [patent_app_type] => utility [patent_app_number] => 10/933062 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 11257 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/442/07442976.pdf [firstpage_image] =>[orig_patent_app_number] => 10933062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 9355173 [patent_doc_number] => 08673706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-18 [patent_title] => 'Methods of forming layers comprising epitaxial silicon' [patent_app_type] => utility [patent_app_number] => 10/932151 [patent_app_country] => US [patent_app_date] => 2004-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 5190 [patent_no_of_claims] => 45 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10932151 [rel_patent_id] =>[rel_patent_doc_number] =>)