
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7104138
[patent_doc_number] => 20050106864
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Process and device for depositing semiconductor layers'
[patent_app_type] => utility
[patent_app_number] => 10/922701
[patent_app_country] => US
[patent_app_date] => 2004-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
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[patent_no_of_words] => 3200
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[pdf_file] => publications/A1/0106/20050106864.pdf
[firstpage_image] =>[orig_patent_app_number] => 10922701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/922701 | Process and device for depositing semiconductor layers | Aug 19, 2004 | Abandoned |
Array
(
[id] => 7197275
[patent_doc_number] => 20050164483
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-07-28
[patent_title] => 'Method of forming solder bump with reduced surface defects'
[patent_app_type] => utility
[patent_app_number] => 10/922172
[patent_app_country] => US
[patent_app_date] => 2004-08-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
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[patent_no_of_words] => 4704
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[pdf_file] => publications/A1/0164/20050164483.pdf
[firstpage_image] =>[orig_patent_app_number] => 10922172
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/922172 | Method of forming solder bump with reduced surface defects | Aug 19, 2004 | Issued |
Array
(
[id] => 496749
[patent_doc_number] => 07208357
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-04-24
[patent_title] => 'Template layer formation'
[patent_app_type] => utility
[patent_app_number] => 10/919922
[patent_app_country] => US
[patent_app_date] => 2004-08-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 5475
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[pdf_file] => patents/07/208/07208357.pdf
[firstpage_image] =>[orig_patent_app_number] => 10919922
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/919922 | Template layer formation | Aug 16, 2004 | Issued |
Array
(
[id] => 694654
[patent_doc_number] => 07071023
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-07-04
[patent_title] => 'Nanotube device structure and methods of fabrication'
[patent_app_type] => utility
[patent_app_number] => 10/918181
[patent_app_country] => US
[patent_app_date] => 2004-08-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 25
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[patent_no_of_words] => 8726
[patent_no_of_claims] => 14
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[pdf_file] => patents/07/071/07071023.pdf
[firstpage_image] =>[orig_patent_app_number] => 10918181
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/918181 | Nanotube device structure and methods of fabrication | Aug 12, 2004 | Issued |
Array
(
[id] => 7122519
[patent_doc_number] => 20050014348
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[patent_kind] => A1
[patent_issue_date] => 2005-01-20
[patent_title] => 'Method of making a semiconductor device having an opening in a solder mask'
[patent_app_type] => utility
[patent_app_number] => 10/917681
[patent_app_country] => US
[patent_app_date] => 2004-08-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
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[pdf_file] => publications/A1/0014/20050014348.pdf
[firstpage_image] =>[orig_patent_app_number] => 10917681
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/917681 | Method of making a semiconductor device having an opening in a solder mask | Aug 11, 2004 | Issued |
Array
(
[id] => 7007140
[patent_doc_number] => 20050060874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-03-24
[patent_title] => 'Method for processing work piece including magnetic material and method for manufacturing magnetic recording medium'
[patent_app_type] => utility
[patent_app_number] => 10/892373
[patent_app_country] => US
[patent_app_date] => 2004-07-16
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[pdf_file] => publications/A1/0060/20050060874.pdf
[firstpage_image] =>[orig_patent_app_number] => 10892373
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/892373 | Method for processing work piece including magnetic material and method for manufacturing magnetic recording medium | Jul 15, 2004 | Abandoned |
Array
(
[id] => 7206104
[patent_doc_number] => 20050258468
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-11-24
[patent_title] => 'Dual work function metal gate integration in semiconductor devices'
[patent_app_type] => utility
[patent_app_number] => 10/890365
[patent_app_country] => US
[patent_app_date] => 2004-07-13
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
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[pdf_file] => publications/A1/0258/20050258468.pdf
[firstpage_image] =>[orig_patent_app_number] => 10890365
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/890365 | Dual work function metal gate integration in semiconductor devices | Jul 12, 2004 | Issued |
Array
(
[id] => 274160
[patent_doc_number] => 07560324
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2009-07-14
[patent_title] => 'Drain extended MOS transistors and methods for making the same'
[patent_app_type] => utility
[patent_app_number] => 10/886842
[patent_app_country] => US
[patent_app_date] => 2004-07-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
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[patent_no_of_words] => 7339
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/560/07560324.pdf
[firstpage_image] =>[orig_patent_app_number] => 10886842
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/886842 | Drain extended MOS transistors and methods for making the same | Jul 7, 2004 | Issued |
Array
(
[id] => 393864
[patent_doc_number] => 07297557
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2007-11-20
[patent_title] => 'Method for chemically bonding Langmuir-Blodgett films to substrates'
[patent_app_type] => utility
[patent_app_number] => 10/880482
[patent_app_country] => US
[patent_app_date] => 2004-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
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[pdf_file] => patents/07/297/07297557.pdf
[firstpage_image] =>[orig_patent_app_number] => 10880482
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/880482 | Method for chemically bonding Langmuir-Blodgett films to substrates | Jun 29, 2004 | Issued |
Array
(
[id] => 975432
[patent_doc_number] => 06933189
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-23
[patent_title] => 'Integration system via metal oxide conversion'
[patent_app_type] => utility
[patent_app_number] => 10/870382
[patent_app_country] => US
[patent_app_date] => 2004-06-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[pdf_file] => patents/06/933/06933189.pdf
[firstpage_image] =>[orig_patent_app_number] => 10870382
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/870382 | Integration system via metal oxide conversion | Jun 15, 2004 | Issued |
Array
(
[id] => 7275799
[patent_doc_number] => 20040235250
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[patent_kind] => A1
[patent_issue_date] => 2004-11-25
[patent_title] => 'Symmetric trench MOSFET device and method of making same'
[patent_app_type] => new
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[pdf_file] => publications/A1/0235/20040235250.pdf
[firstpage_image] =>[orig_patent_app_number] => 10869802
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/869802 | Symmetric trench MOSFET device and method of making same | Jun 15, 2004 | Abandoned |
Array
(
[id] => 7329023
[patent_doc_number] => 20040253824
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[patent_title] => 'Arrangement for monitoring a thickness of a layer depositing on a sidewall of a processing chamber'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/861902 | Arrangement for monitoring a thickness of a layer depositing on a sidewall of a processing chamber | Jun 3, 2004 | Abandoned |
Array
(
[id] => 7174281
[patent_doc_number] => 20040201086
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[patent_issue_date] => 2004-10-14
[patent_title] => 'Flip chip in leaded molded package with two dies'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/834752 | Flip chip in leaded molded package with two dies | Apr 27, 2004 | Issued |
Array
(
[id] => 7069685
[patent_doc_number] => 20050245070
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[patent_kind] => A1
[patent_issue_date] => 2005-11-03
[patent_title] => 'BARRIER FOR INTERCONNECT AND METHOD'
[patent_app_type] => utility
[patent_app_number] => 10/709321
[patent_app_country] => US
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Array
(
[id] => 7462085
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[patent_title] => 'Divot reduction in SIMOX layers'
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[firstpage_image] =>[orig_patent_app_number] => 10832215
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/832215 | Divot reduction in SIMOX layers | Apr 25, 2004 | Issued |
Array
(
[id] => 1062767
[patent_doc_number] => 06849511
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[patent_issue_date] => 2005-02-01
[patent_title] => 'Semiconductor device and method for fabricating the same including interconnection of two electrodes'
[patent_app_type] => utility
[patent_app_number] => 10/819230
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/819230 | Semiconductor device and method for fabricating the same including interconnection of two electrodes | Apr 6, 2004 | Issued |
Array
(
[id] => 7334204
[patent_doc_number] => 20040188823
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[patent_issue_date] => 2004-09-30
[patent_title] => 'JOGGING STRUCTURE FOR WIRING TRANSLATION BETWEEN GRIDS WITH NON-INTEGRAL PITCH RATIOS IN CHIP CARRIER MODULES'
[patent_app_type] => new
[patent_app_number] => 10/709012
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/709012 | Jogging structure for wiring translation between grids with non-integral pitch ratios in chip carrier modules | Apr 6, 2004 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/818425 | Semiconductor device and method of manufacturing the same comprising thin film containing low concentration of hydrogen | Apr 4, 2004 | Issued |
Array
(
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/810031 | Termination for trench MIS device having implanted drain-drift region | Mar 25, 2004 | Issued |