
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7393534
[patent_doc_number] => 20040173847
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-09
[patent_title] => 'Method of controlling floating body effects in an asymmetrical SOI device'
[patent_app_type] => new
[patent_app_number] => 10/805442
[patent_app_country] => US
[patent_app_date] => 2004-03-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 3461
[patent_no_of_claims] => 22
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[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0173/20040173847.pdf
[firstpage_image] =>[orig_patent_app_number] => 10805442
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/805442 | Method of controlling floating body effects in an asymmetrical SOI device | Mar 21, 2004 | Abandoned |
Array
(
[id] => 988146
[patent_doc_number] => 06921701
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-07-26
[patent_title] => 'Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure'
[patent_app_type] => utility
[patent_app_number] => 10/801731
[patent_app_country] => US
[patent_app_date] => 2004-03-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/06/921/06921701.pdf
[firstpage_image] =>[orig_patent_app_number] => 10801731
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/801731 | Method of manufacturing and structure of semiconductor device (DEMOS) with field oxide structure | Mar 14, 2004 | Issued |
Array
(
[id] => 7150154
[patent_doc_number] => 20040171224
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-09-02
[patent_title] => 'Method for fabricating a semiconductor device having an insulation film with reduced water content'
[patent_app_type] => new
[patent_app_number] => 10/793862
[patent_app_country] => US
[patent_app_date] => 2004-03-08
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[firstpage_image] =>[orig_patent_app_number] => 10793862
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/793862 | Method for fabricating a semiconductor device having an insulation film with reduced water content | Mar 7, 2004 | Issued |
Array
(
[id] => 7462260
[patent_doc_number] => 20040197965
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-10-07
[patent_title] => 'Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor'
[patent_app_type] => new
[patent_app_number] => 10/792691
[patent_app_country] => US
[patent_app_date] => 2004-03-05
[patent_effective_date] => 0000-00-00
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/792691 | Method for forming an SOI substrate, vertical transistor and memory cell with vertical transistor | Mar 4, 2004 | Issued |
Array
(
[id] => 7176698
[patent_doc_number] => 20050189632
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-09-01
[patent_title] => 'Sealed three dimensional metal bonded integrated circuits'
[patent_app_type] => utility
[patent_app_number] => 10/791492
[patent_app_country] => US
[patent_app_date] => 2004-03-01
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0189/20050189632.pdf
[firstpage_image] =>[orig_patent_app_number] => 10791492
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/791492 | Sealed three dimensional metal bonded integrated circuits | Feb 29, 2004 | Issued |
Array
(
[id] => 990723
[patent_doc_number] => 06919249
[patent_country] => US
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[patent_issue_date] => 2005-07-19
[patent_title] => 'Semiconductor device and its manufacturing method comprising a trench gate'
[patent_app_type] => utility
[patent_app_number] => 10/778072
[patent_app_country] => US
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[pdf_file] => patents/06/919/06919249.pdf
[firstpage_image] =>[orig_patent_app_number] => 10778072
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/778072 | Semiconductor device and its manufacturing method comprising a trench gate | Feb 16, 2004 | Issued |
Array
(
[id] => 7677537
[patent_doc_number] => 20040152289
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-08-05
[patent_title] => 'Semiconductor device with mushroom electrode and manufacture method thereof'
[patent_app_type] => new
[patent_app_number] => 10/768092
[patent_app_country] => US
[patent_app_date] => 2004-02-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
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[patent_no_of_words] => 8287
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[pdf_file] => publications/A1/0152/20040152289.pdf
[firstpage_image] =>[orig_patent_app_number] => 10768092
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/768092 | Semiconductor device with mushroom electrode and manufacture method thereof | Feb 1, 2004 | Issued |
Array
(
[id] => 7151394
[patent_doc_number] => 20050081349
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-04-21
[patent_title] => 'Embedded capacitor structure in circuit board and method for fabricating the same'
[patent_app_type] => utility
[patent_app_number] => 10/739371
[patent_app_country] => US
[patent_app_date] => 2003-12-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 4
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[patent_no_of_words] => 2412
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[pdf_file] => publications/A1/0081/20050081349.pdf
[firstpage_image] =>[orig_patent_app_number] => 10739371
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/739371 | Embedded capacitor structure in circuit board and method for fabricating the same | Dec 16, 2003 | Abandoned |
Array
(
[id] => 7104099
[patent_doc_number] => 20050106825
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2005-05-19
[patent_title] => 'Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor'
[patent_app_type] => utility
[patent_app_number] => 10/714271
[patent_app_country] => US
[patent_app_date] => 2003-11-13
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[patent_drawing_sheets_cnt] => 28
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[pdf_file] => publications/A1/0106/20050106825.pdf
[firstpage_image] =>[orig_patent_app_number] => 10714271
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/714271 | Method of fabricating a lateral double-diffused mosfet (LDMOS) transistor and a conventional CMOS transistor | Nov 12, 2003 | Issued |
Array
(
[id] => 7365325
[patent_doc_number] => 20040092109
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-05-13
[patent_title] => 'Semiconductor device and method for making the device having an electrically modulated conduction channel'
[patent_app_type] => new
[patent_app_number] => 10/697012
[patent_app_country] => US
[patent_app_date] => 2003-10-31
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[firstpage_image] =>[orig_patent_app_number] => 10697012
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697012 | Semiconductor device and method for making the device having an electrically modulated conduction channel | Oct 30, 2003 | Abandoned |
Array
(
[id] => 7365094
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[patent_issue_date] => 2004-05-13
[patent_title] => 'Semiconductor device and manufacturing method thereof'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/697045 | Semiconductor device and manufacturing method thereof | Oct 30, 2003 | Abandoned |
Array
(
[id] => 7083329
[patent_doc_number] => 20050048709
[patent_country] => US
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[patent_issue_date] => 2005-03-03
[patent_title] => 'Multiple operating voltage vertical replacement-gate (VRG) transistor'
[patent_app_type] => utility
[patent_app_number] => 10/684713
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[firstpage_image] =>[orig_patent_app_number] => 10684713
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684713 | Multiple operating voltage vertical replacement-gate (VRG) transistor | Oct 13, 2003 | Issued |
Array
(
[id] => 7383266
[patent_doc_number] => 20040082133
[patent_country] => US
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[patent_issue_date] => 2004-04-29
[patent_title] => 'Eliminating substrate noise by an electrically isolated high-voltage I/O transistor'
[patent_app_type] => new
[patent_app_number] => 10/684948
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[firstpage_image] =>[orig_patent_app_number] => 10684948
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/684948 | Eliminating substrate noise by an electrically isolated high-voltage I/O transistor | Oct 13, 2003 | Issued |
Array
(
[id] => 7204623
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[patent_title] => 'Nanostructure field emission cathode material within a device'
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[patent_app_number] => 10/681565
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Array
(
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[patent_title] => '[METHOD OF FORMING DUAL-IMPLANTED GATE AND STRUCTURE FORMED BY THE SAME]'
[patent_app_type] => new
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/605426 | [METHOD OF FORMING DUAL-IMPLANTED GATE AND STRUCTURE FORMED BY THE SAME] | Sep 29, 2003 | Abandoned |
Array
(
[id] => 769102
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[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-02-28
[patent_title] => 'Depletion drain-extended MOS transistors and methods for making the same'
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[patent_app_number] => 10/669111
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/669111 | Depletion drain-extended MOS transistors and methods for making the same | Sep 22, 2003 | Issued |
Array
(
[id] => 760912
[patent_doc_number] => 07012020
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[patent_issue_date] => 2006-03-14
[patent_title] => 'Multi-layered metal routing technique'
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[patent_app_number] => 10/661042
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/661042 | Multi-layered metal routing technique | Sep 11, 2003 | Issued |
Array
(
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[patent_title] => 'Process for making a gate for a short channel CMOS transistor structure'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/570852 | Method and device of field effect transistor including a base shorted to a source region | Sep 4, 2003 | Issued |
Array
(
[id] => 7130150
[patent_doc_number] => 20040041179
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[patent_title] => 'SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME'
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[firstpage_image] =>[orig_patent_app_number] => 10655022
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/655022 | Semiconductor device and method of manufacturing the same including a dual layer raised source and drain | Sep 4, 2003 | Issued |