Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7313617 [patent_doc_number] => 20040033665 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-19 [patent_title] => 'Structure and method of controlling short-channel effect of very short channel MOSFET' [patent_app_type] => new [patent_app_number] => 10/641522 [patent_app_country] => US [patent_app_date] => 2003-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4568 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0033/20040033665.pdf [firstpage_image] =>[orig_patent_app_number] => 10641522 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/641522
Structure and method of controlling short-channel effect of very short channel MOSFET Aug 14, 2003 Abandoned
Array ( [id] => 659701 [patent_doc_number] => 07105916 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Inlet for an electronic tag' [patent_app_type] => utility [patent_app_number] => 10/634751 [patent_app_country] => US [patent_app_date] => 2003-08-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 35 [patent_no_of_words] => 7598 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105916.pdf [firstpage_image] =>[orig_patent_app_number] => 10634751 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/634751
Inlet for an electronic tag Aug 5, 2003 Issued
Array ( [id] => 534297 [patent_doc_number] => 07176096 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-02-13 [patent_title] => 'Transistor gate and local interconnect' [patent_app_type] => utility [patent_app_number] => 10/631921 [patent_app_country] => US [patent_app_date] => 2003-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3985 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/176/07176096.pdf [firstpage_image] =>[orig_patent_app_number] => 10631921 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/631921
Transistor gate and local interconnect Jul 30, 2003 Issued
Array ( [id] => 8232665 [patent_doc_number] => 08198105 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-06-12 [patent_title] => 'Monitor for variation of critical dimensions (CDs) of reticles' [patent_app_type] => utility [patent_app_number] => 10/630332 [patent_app_country] => US [patent_app_date] => 2003-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3731 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/198/08198105.pdf [firstpage_image] =>[orig_patent_app_number] => 10630332 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/630332
Monitor for variation of critical dimensions (CDs) of reticles Jul 29, 2003 Issued
Array ( [id] => 7204931 [patent_doc_number] => 20040070036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-15 [patent_title] => 'ULSI MOS with high dielectric constant gate insulator' [patent_app_type] => new [patent_app_number] => 10/622652 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2769 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0070/20040070036.pdf [firstpage_image] =>[orig_patent_app_number] => 10622652 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622652
ULSI MOS with high dielectric constant gate insulator Jul 20, 2003 Issued
Array ( [id] => 7203773 [patent_doc_number] => 20040087091 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-06 [patent_title] => 'ULSI MOS with high dielectric constant gate insulator' [patent_app_type] => new [patent_app_number] => 10/622484 [patent_app_country] => US [patent_app_date] => 2003-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2749 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20040087091.pdf [firstpage_image] =>[orig_patent_app_number] => 10622484 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/622484
ULSI MOS with high dielectric constant gate insulator Jul 20, 2003 Abandoned
Array ( [id] => 7144364 [patent_doc_number] => 20050118837 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-02 [patent_title] => 'Method to form ultra high quality silicon-containing compound layers' [patent_app_type] => utility [patent_app_number] => 10/623482 [patent_app_country] => US [patent_app_date] => 2003-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 13945 [patent_no_of_claims] => 46 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20050118837.pdf [firstpage_image] =>[orig_patent_app_number] => 10623482 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/623482
Method to form ultra high quality silicon-containing compound layers Jul 17, 2003 Issued
Array ( [id] => 1014606 [patent_doc_number] => 06893948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-17 [patent_title] => 'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size' [patent_app_type] => utility [patent_app_number] => 10/616962 [patent_app_country] => US [patent_app_date] => 2003-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2518 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893948.pdf [firstpage_image] =>[orig_patent_app_number] => 10616962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/616962
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Jul 10, 2003 Issued
Array ( [id] => 7365160 [patent_doc_number] => 20040092071 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-05-13 [patent_title] => 'Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry' [patent_app_type] => new [patent_app_number] => 10/611602 [patent_app_country] => US [patent_app_date] => 2003-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2444 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20040092071.pdf [firstpage_image] =>[orig_patent_app_number] => 10611602 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/611602
Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry Jun 29, 2003 Issued
Array ( [id] => 7429533 [patent_doc_number] => 20040266115 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-30 [patent_title] => 'Method of making a gate electrode on a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/603361 [patent_app_country] => US [patent_app_date] => 2003-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3826 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0266/20040266115.pdf [firstpage_image] =>[orig_patent_app_number] => 10603361 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/603361
Method of making a gate electrode on a semiconductor device Jun 24, 2003 Abandoned
Array ( [id] => 1115519 [patent_doc_number] => 06800509 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET' [patent_app_type] => B1 [patent_app_number] => 10/601651 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 15 [patent_no_of_words] => 2069 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800509.pdf [firstpage_image] =>[orig_patent_app_number] => 10601651 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/601651
Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET Jun 23, 2003 Issued
Array ( [id] => 7675143 [patent_doc_number] => 20040126975 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-07-01 [patent_title] => 'Double gate semiconductor device having separate gates' [patent_app_type] => new [patent_app_number] => 10/602061 [patent_app_country] => US [patent_app_date] => 2003-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3367 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0126/20040126975.pdf [firstpage_image] =>[orig_patent_app_number] => 10602061 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/602061
Double gate semiconductor device having separate gates Jun 23, 2003 Abandoned
Array ( [id] => 1071853 [patent_doc_number] => 06841437 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method of forming a vertical power semiconductor device and structure therefor' [patent_app_type] => utility [patent_app_number] => 10/464971 [patent_app_country] => US [patent_app_date] => 2003-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1994 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841437.pdf [firstpage_image] =>[orig_patent_app_number] => 10464971 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/464971
Method of forming a vertical power semiconductor device and structure therefor Jun 19, 2003 Issued
Array ( [id] => 1014568 [patent_doc_number] => 06893910 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-17 [patent_title] => 'One step deposition method for high-k dielectric and metal gate electrode' [patent_app_type] => utility [patent_app_number] => 10/462670 [patent_app_country] => US [patent_app_date] => 2003-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 3036 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/893/06893910.pdf [firstpage_image] =>[orig_patent_app_number] => 10462670 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/462670
One step deposition method for high-k dielectric and metal gate electrode Jun 16, 2003 Issued
Array ( [id] => 7365753 [patent_doc_number] => 20040005766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-08 [patent_title] => 'METHOD OF FORMING A BOTTOM OXIDE LAYER IN A TRENCH' [patent_app_type] => new [patent_app_number] => 10/453771 [patent_app_country] => US [patent_app_date] => 2003-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2735 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20040005766.pdf [firstpage_image] =>[orig_patent_app_number] => 10453771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/453771
Method of forming a bottom oxide layer in a trench Jun 1, 2003 Issued
Array ( [id] => 679670 [patent_doc_number] => 07084034 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-08-01 [patent_title] => 'High voltage MOS-gated power device and related manufacturing process' [patent_app_type] => utility [patent_app_number] => 10/430771 [patent_app_country] => US [patent_app_date] => 2003-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 3646 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/084/07084034.pdf [firstpage_image] =>[orig_patent_app_number] => 10430771 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/430771
High voltage MOS-gated power device and related manufacturing process May 5, 2003 Issued
Array ( [id] => 1101666 [patent_doc_number] => 06815300 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Method for manufacturing semiconductor device having increased effective channel length' [patent_app_type] => B2 [patent_app_number] => 10/427172 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 28 [patent_no_of_words] => 7155 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815300.pdf [firstpage_image] =>[orig_patent_app_number] => 10427172 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/427172
Method for manufacturing semiconductor device having increased effective channel length Apr 29, 2003 Issued
Array ( [id] => 7135197 [patent_doc_number] => 20040043595 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes' [patent_app_type] => new [patent_app_number] => 10/426562 [patent_app_country] => US [patent_app_date] => 2003-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4188 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043595.pdf [firstpage_image] =>[orig_patent_app_number] => 10426562 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/426562
Methods of forming integrated circuits with thermal oxide layers on side walls of gate electrodes wherein the source and drain are higher than the gate electrode Apr 29, 2003 Issued
Array ( [id] => 508362 [patent_doc_number] => 07198962 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-04-03 [patent_title] => 'Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step' [patent_app_type] => utility [patent_app_number] => 10/411283 [patent_app_country] => US [patent_app_date] => 2003-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9102 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/198/07198962.pdf [firstpage_image] =>[orig_patent_app_number] => 10411283 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/411283
Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step Apr 10, 2003 Issued
Array ( [id] => 6865272 [patent_doc_number] => 20030190798 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-10-09 [patent_title] => 'Method for manufacturing a semiconductor device having a layered gate electrode' [patent_app_type] => new [patent_app_number] => 10/406311 [patent_app_country] => US [patent_app_date] => 2003-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1951 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20030190798.pdf [firstpage_image] =>[orig_patent_app_number] => 10406311 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/406311
Method for manufacturing a semiconductor device having a layered gate electrode Apr 3, 2003 Issued
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