
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 7313617
[patent_doc_number] => 20040033665
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2004-02-19
[patent_title] => 'Structure and method of controlling short-channel effect of very short channel MOSFET'
[patent_app_type] => new
[patent_app_number] => 10/641522
[patent_app_country] => US
[patent_app_date] => 2003-08-15
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0033/20040033665.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/641522 | Structure and method of controlling short-channel effect of very short channel MOSFET | Aug 14, 2003 | Abandoned |
Array
(
[id] => 659701
[patent_doc_number] => 07105916
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[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Inlet for an electronic tag'
[patent_app_type] => utility
[patent_app_number] => 10/634751
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[patent_app_date] => 2003-08-06
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/105/07105916.pdf
[firstpage_image] =>[orig_patent_app_number] => 10634751
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/634751 | Inlet for an electronic tag | Aug 5, 2003 | Issued |
Array
(
[id] => 534297
[patent_doc_number] => 07176096
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2007-02-13
[patent_title] => 'Transistor gate and local interconnect'
[patent_app_type] => utility
[patent_app_number] => 10/631921
[patent_app_country] => US
[patent_app_date] => 2003-07-31
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/631921 | Transistor gate and local interconnect | Jul 30, 2003 | Issued |
Array
(
[id] => 8232665
[patent_doc_number] => 08198105
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[patent_kind] => B2
[patent_issue_date] => 2012-06-12
[patent_title] => 'Monitor for variation of critical dimensions (CDs) of reticles'
[patent_app_type] => utility
[patent_app_number] => 10/630332
[patent_app_country] => US
[patent_app_date] => 2003-07-30
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/630332 | Monitor for variation of critical dimensions (CDs) of reticles | Jul 29, 2003 | Issued |
Array
(
[id] => 7204931
[patent_doc_number] => 20040070036
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[patent_title] => 'ULSI MOS with high dielectric constant gate insulator'
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[pdf_file] => publications/A1/0070/20040070036.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622652 | ULSI MOS with high dielectric constant gate insulator | Jul 20, 2003 | Issued |
Array
(
[id] => 7203773
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[patent_issue_date] => 2004-05-06
[patent_title] => 'ULSI MOS with high dielectric constant gate insulator'
[patent_app_type] => new
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[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/622484 | ULSI MOS with high dielectric constant gate insulator | Jul 20, 2003 | Abandoned |
Array
(
[id] => 7144364
[patent_doc_number] => 20050118837
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[patent_title] => 'Method to form ultra high quality silicon-containing compound layers'
[patent_app_type] => utility
[patent_app_number] => 10/623482
[patent_app_country] => US
[patent_app_date] => 2003-07-18
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0118/20050118837.pdf
[firstpage_image] =>[orig_patent_app_number] => 10623482
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/623482 | Method to form ultra high quality silicon-containing compound layers | Jul 17, 2003 | Issued |
Array
(
[id] => 1014606
[patent_doc_number] => 06893948
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-17
[patent_title] => 'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size'
[patent_app_type] => utility
[patent_app_number] => 10/616962
[patent_app_country] => US
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[pdf_file] => patents/06/893/06893948.pdf
[firstpage_image] =>[orig_patent_app_number] => 10616962
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/616962 | Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size | Jul 10, 2003 | Issued |
Array
(
[id] => 7365160
[patent_doc_number] => 20040092071
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[patent_issue_date] => 2004-05-13
[patent_title] => 'Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/611602 | Semiconductor processing methods of forming dynamic random access memory (DRAM) circuitry | Jun 29, 2003 | Issued |
Array
(
[id] => 7429533
[patent_doc_number] => 20040266115
[patent_country] => US
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[patent_issue_date] => 2004-12-30
[patent_title] => 'Method of making a gate electrode on a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/603361
[patent_app_country] => US
[patent_app_date] => 2003-06-25
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/603361 | Method of making a gate electrode on a semiconductor device | Jun 24, 2003 | Abandoned |
Array
(
[id] => 1115519
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[patent_title] => 'Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET'
[patent_app_type] => B1
[patent_app_number] => 10/601651
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/601651 | Process for enhancement of voltage endurance and reduction of parasitic capacitance for a trench power MOSFET | Jun 23, 2003 | Issued |
Array
(
[id] => 7675143
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[patent_title] => 'Double gate semiconductor device having separate gates'
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Array
(
[id] => 1071853
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[patent_title] => 'Method of forming a vertical power semiconductor device and structure therefor'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/464971 | Method of forming a vertical power semiconductor device and structure therefor | Jun 19, 2003 | Issued |
Array
(
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[patent_title] => 'One step deposition method for high-k dielectric and metal gate electrode'
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Array
(
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[patent_title] => 'METHOD OF FORMING A BOTTOM OXIDE LAYER IN A TRENCH'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/453771 | Method of forming a bottom oxide layer in a trench | Jun 1, 2003 | Issued |
Array
(
[id] => 679670
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[patent_title] => 'High voltage MOS-gated power device and related manufacturing process'
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Array
(
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[patent_title] => 'Method for manufacturing semiconductor device having increased effective channel length'
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Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/406311 | Method for manufacturing a semiconductor device having a layered gate electrode | Apr 3, 2003 | Issued |