Scott R. Wilson

Array ( [id] => 1175216 [patent_doc_number] => 06746925 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'High-k dielectric bird\'s beak optimizations using in-situ O2 plasma oxidation' [patent_app_type] => B1 [patent_app_number] => 10/397451 [patent_app_country] => US [patent_app_date] => 2003-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 3128 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746925.pdf [firstpage_image] =>[orig_patent_app_number] => 10397451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6770067 [patent_doc_number] => 20030216007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-20 [patent_title] => 'Method for shallow trench isolation fabrication and partial oxide layer removal' [patent_app_type] => new [patent_app_number] => 10/394681 [patent_app_country] => US [patent_app_date] => 2003-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1544 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0216/20030216007.pdf [firstpage_image] =>[orig_patent_app_number] => 10394681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1116875 [patent_doc_number] => 06800885 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-10-05 [patent_title] => 'Asymmetrical double gate or all-around gate MOSFET devices and methods for making same' [patent_app_type] => B1 [patent_app_number] => 10/385652 [patent_app_country] => US [patent_app_date] => 2003-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 4070 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/800/06800885.pdf [firstpage_image] =>[orig_patent_app_number] => 10385652 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7673279 [patent_doc_number] => 20040180500 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-16 [patent_title] => 'MOSFET power transistors and methods' [patent_app_type] => new [patent_app_number] => 10/385807 [patent_app_country] => US [patent_app_date] => 2003-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3787 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0180/20040180500.pdf [firstpage_image] =>[orig_patent_app_number] => 10385807 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7406679 [patent_doc_number] => 20040175907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-09-09 [patent_title] => 'Method of fabricating a salicided device using a dummy dielectric layer between the source/drain and the gate electrode' [patent_app_type] => new [patent_app_number] => 10/383711 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3829 [patent_no_of_claims] => 65 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20040175907.pdf [firstpage_image] =>[orig_patent_app_number] => 10383711 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 707539 [patent_doc_number] => 07060520 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-06-13 [patent_title] => 'Piezoelectric device and cover sealing method and apparatus therefor, cellular phone apparatus using piezoelectric device and electronic apparatus using piezoelectric device' [patent_app_type] => utility [patent_app_number] => 10/382840 [patent_app_country] => US [patent_app_date] => 2003-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 32 [patent_no_of_words] => 13924 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/060/07060520.pdf [firstpage_image] =>[orig_patent_app_number] => 10382840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6845371 [patent_doc_number] => 20030164538 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-04 [patent_title] => 'Semiconductor device' [patent_app_type] => new [patent_app_number] => 10/275792 [patent_app_country] => US [patent_app_date] => 2003-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2559 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0164/20030164538.pdf [firstpage_image] =>[orig_patent_app_number] => 10275792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1017973 [patent_doc_number] => 06890867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-10 [patent_title] => 'Transistor fabrication methods comprising selective wet-oxidation' [patent_app_type] => utility [patent_app_number] => 10/375721 [patent_app_country] => US [patent_app_date] => 2003-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3278 [patent_no_of_claims] => 75 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/890/06890867.pdf [firstpage_image] =>[orig_patent_app_number] => 10375721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1056383 [patent_doc_number] => 06855606 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-02-15 [patent_title] => 'Semiconductor nano-rod devices' [patent_app_type] => utility [patent_app_number] => 10/370792 [patent_app_country] => US [patent_app_date] => 2003-02-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 16 [patent_no_of_words] => 3975 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/855/06855606.pdf [firstpage_image] =>[orig_patent_app_number] => 10370792 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1123394 [patent_doc_number] => 06794263 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-09-21 [patent_title] => 'Method of manufacturing a semiconductor device including alignment mark' [patent_app_type] => B1 [patent_app_number] => 10/367931 [patent_app_country] => US [patent_app_date] => 2003-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 36 [patent_no_of_words] => 4325 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/794/06794263.pdf [firstpage_image] =>[orig_patent_app_number] => 10367931 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1172697 [patent_doc_number] => 06750127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method for fabricating a semiconductor device using amorphous carbon having improved etch resistance' [patent_app_type] => B1 [patent_app_number] => 10/367407 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 2245 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750127.pdf [firstpage_image] =>[orig_patent_app_number] => 10367407 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1270195 [patent_doc_number] => 06653204 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of forming a shallow trench isolation structure' [patent_app_type] => B1 [patent_app_number] => 10/248749 [patent_app_country] => US [patent_app_date] => 2003-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1696 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/653/06653204.pdf [firstpage_image] =>[orig_patent_app_number] => 10248749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6983463 [patent_doc_number] => 20050153533 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-07-14 [patent_title] => 'Semiconductor manufacturing method and semiconductor manufacturing apparatus' [patent_app_type] => utility [patent_app_number] => 10/503131 [patent_app_country] => US [patent_app_date] => 2003-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6399 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0153/20050153533.pdf [firstpage_image] =>[orig_patent_app_number] => 10503131 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1031032 [patent_doc_number] => 06878583 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Integration method to enhance p+ gate activation' [patent_app_type] => utility [patent_app_number] => 10/358632 [patent_app_country] => US [patent_app_date] => 2003-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2177 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878583.pdf [firstpage_image] =>[orig_patent_app_number] => 10358632 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 509406 [patent_doc_number] => 07195937 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-03-27 [patent_title] => 'Method for measuring withstand voltage of semiconductor epitaxial wafer and semiconductor epitaxial wafer' [patent_app_type] => utility [patent_app_number] => 10/484001 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 3767 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/195/07195937.pdf [firstpage_image] =>[orig_patent_app_number] => 10484001 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5705320 [patent_doc_number] => 20060194368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-08-31 [patent_title] => 'Thin film translator array panel and a method for manufacturing the panel' [patent_app_type] => utility [patent_app_number] => 10/531442 [patent_app_country] => US [patent_app_date] => 2003-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 32 [patent_no_of_words] => 5772 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0194/20060194368.pdf [firstpage_image] =>[orig_patent_app_number] => 10531442 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 7611031 [patent_doc_number] => 06841826 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-01-11 [patent_title] => 'Low-GIDL MOSFET structure and method for fabrication' [patent_app_type] => utility [patent_app_number] => 10/345472 [patent_app_country] => US [patent_app_date] => 2003-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2275 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/841/06841826.pdf [firstpage_image] =>[orig_patent_app_number] => 10345472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1031040 [patent_doc_number] => 06878592 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-04-12 [patent_title] => 'Selective epitaxy to improve silicidation' [patent_app_type] => utility [patent_app_number] => 10/341772 [patent_app_country] => US [patent_app_date] => 2003-01-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 3225 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878592.pdf [firstpage_image] =>[orig_patent_app_number] => 10341772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6659754 [patent_doc_number] => 20030134517 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 10/337338 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9037 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134517.pdf [firstpage_image] =>[orig_patent_app_number] => 10337338 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6668984 [patent_doc_number] => 20030113968 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Methods to form electronic devices and methods to form a material over a semiconductive substrate' [patent_app_type] => new [patent_app_number] => 10/338523 [patent_app_country] => US [patent_app_date] => 2003-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4412 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 20 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113968.pdf [firstpage_image] =>[orig_patent_app_number] => 10338523 [rel_patent_id] =>[rel_patent_doc_number] =>)