Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6765367 [patent_doc_number] => 20030099766 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-29 [patent_title] => 'Semiconductor device with selectable gate thickness and method of manufacturing such devices' [patent_app_type] => new [patent_app_number] => 10/286427 [patent_app_country] => US [patent_app_date] => 2002-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8184 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0099/20030099766.pdf [firstpage_image] =>[orig_patent_app_number] => 10286427 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/286427
Semiconductor device with selectable gate thickness and method of manufacturing such devices Oct 29, 2002 Issued
Array ( [id] => 7383118 [patent_doc_number] => 20040082107 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-29 [patent_title] => 'Flip-chip system and method of making same' [patent_app_type] => new [patent_app_number] => 10/281844 [patent_app_country] => US [patent_app_date] => 2002-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5625 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20040082107.pdf [firstpage_image] =>[orig_patent_app_number] => 10281844 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/281844
Flip-chip system and method of making same Oct 27, 2002 Issued
Array ( [id] => 487920 [patent_doc_number] => 07214289 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-05-08 [patent_title] => 'Method and apparatus for wall film monitoring' [patent_app_type] => utility [patent_app_number] => 10/493138 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4788 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/214/07214289.pdf [firstpage_image] =>[orig_patent_app_number] => 10493138 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/493138
Method and apparatus for wall film monitoring Oct 23, 2002 Issued
Array ( [id] => 6870159 [patent_doc_number] => 20030082848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-01 [patent_title] => 'Semiconductor device and manufacturing method' [patent_app_type] => new [patent_app_number] => 10/279686 [patent_app_country] => US [patent_app_date] => 2002-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4710 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0082/20030082848.pdf [firstpage_image] =>[orig_patent_app_number] => 10279686 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/279686
Semiconductor device and manufacturing method Oct 23, 2002 Abandoned
Array ( [id] => 1302189 [patent_doc_number] => 06624455 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-09-23 [patent_title] => 'Semiconductor device and method of manufacturing the same including drain pinned along channel width' [patent_app_type] => B2 [patent_app_number] => 10/278441 [patent_app_country] => US [patent_app_date] => 2002-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 6733 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/624/06624455.pdf [firstpage_image] =>[orig_patent_app_number] => 10278441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/278441
Semiconductor device and method of manufacturing the same including drain pinned along channel width Oct 21, 2002 Issued
Array ( [id] => 7167110 [patent_doc_number] => 20040077112 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-22 [patent_title] => 'Conductive component manufacturing process employing an ink jet printer' [patent_app_type] => new [patent_app_number] => 10/273782 [patent_app_country] => US [patent_app_date] => 2002-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 2177 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20040077112.pdf [firstpage_image] =>[orig_patent_app_number] => 10273782 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/273782
Conductive component manufacturing process employing an ink jet printer Oct 17, 2002 Abandoned
Array ( [id] => 1249121 [patent_doc_number] => 06674144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-06 [patent_title] => 'Process for forming damascene-type isolation structure for integrated circuit' [patent_app_type] => B1 [patent_app_number] => 10/269125 [patent_app_country] => US [patent_app_date] => 2002-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2476 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 476 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/674/06674144.pdf [firstpage_image] =>[orig_patent_app_number] => 10269125 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/269125
Process for forming damascene-type isolation structure for integrated circuit Oct 10, 2002 Issued
Array ( [id] => 7242994 [patent_doc_number] => 20040257719 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-12-23 [patent_title] => 'Magnetoresistive effect element, magnetic memory element magnetic memory device and manufacturing methods thereof' [patent_app_type] => new [patent_app_number] => 10/492147 [patent_app_country] => US [patent_app_date] => 2004-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 14850 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 49 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0257/20040257719.pdf [firstpage_image] =>[orig_patent_app_number] => 10492147 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/492147
Magnetoresistive effect element, magnetic memory element magnetic memory device and manufacturing methods thereof Oct 10, 2002 Issued
Array ( [id] => 6817905 [patent_doc_number] => 20030068863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-10 [patent_title] => 'Method for fabricating a power semiconductor device having a floating island voltage sustaining layer' [patent_app_type] => new [patent_app_number] => 10/264951 [patent_app_country] => US [patent_app_date] => 2002-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3211 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20030068863.pdf [firstpage_image] =>[orig_patent_app_number] => 10264951 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/264951
Method for fabricating a power semiconductor device having a floating island voltage sustaining layer Oct 3, 2002 Issued
Array ( [id] => 7450287 [patent_doc_number] => 20040067631 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Reduction of seed layer roughness for use in forming SiGe gate electrode' [patent_app_type] => new [patent_app_number] => 10/263521 [patent_app_country] => US [patent_app_date] => 2002-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6056 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067631.pdf [firstpage_image] =>[orig_patent_app_number] => 10263521 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263521
Reduction of seed layer roughness for use in forming SiGe gate electrode Oct 2, 2002 Abandoned
Array ( [id] => 7450182 [patent_doc_number] => 20040067620 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-04-08 [patent_title] => 'Method for moat nitride pull back for shallow trench isolation' [patent_app_type] => new [patent_app_number] => 10/263511 [patent_app_country] => US [patent_app_date] => 2002-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2351 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0067/20040067620.pdf [firstpage_image] =>[orig_patent_app_number] => 10263511 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/263511
Method for moat nitride pull back for shallow trench isolation Oct 1, 2002 Issued
Array ( [id] => 7269959 [patent_doc_number] => 20040058477 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-25 [patent_title] => 'Integrated circuit package and manufacturing method therefor' [patent_app_type] => new [patent_app_number] => 10/251231 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3132 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0058/20040058477.pdf [firstpage_image] =>[orig_patent_app_number] => 10251231 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251231
Integrated circuit package and manufacturing method therefor with unique interconnector Sep 18, 2002 Issued
Array ( [id] => 7314360 [patent_doc_number] => 20040222520 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-11-11 [patent_title] => 'INTEGRATED CIRCUIT PACKAGE WITH FLAT METAL BUMP AND MANUFACTURING METHOD THEREFOR' [patent_app_type] => new [patent_app_number] => 10/251512 [patent_app_country] => US [patent_app_date] => 2002-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2436 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0222/20040222520.pdf [firstpage_image] =>[orig_patent_app_number] => 10251512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/251512
INTEGRATED CIRCUIT PACKAGE WITH FLAT METAL BUMP AND MANUFACTURING METHOD THEREFOR Sep 18, 2002 Abandoned
Array ( [id] => 6813739 [patent_doc_number] => 20030073289 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-17 [patent_title] => 'Trench-gate semiconductor devices and their manufacture' [patent_app_type] => new [patent_app_number] => 10/246171 [patent_app_country] => US [patent_app_date] => 2002-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6623 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20030073289.pdf [firstpage_image] =>[orig_patent_app_number] => 10246171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/246171
Trench-gate semiconductor devices and their manufacture Sep 17, 2002 Abandoned
Array ( [id] => 6696989 [patent_doc_number] => 20030109183 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-12 [patent_title] => 'Process for bonding and electrically connecting microsystems integrated in several distinct substrates' [patent_app_type] => new [patent_app_number] => 10/243972 [patent_app_country] => US [patent_app_date] => 2002-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2712 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 17 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0109/20030109183.pdf [firstpage_image] =>[orig_patent_app_number] => 10243972 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/243972
Process for bonding and electrically connecting microsystems integrated in several distinct substrates Sep 11, 2002 Abandoned
Array ( [id] => 968461 [patent_doc_number] => 06939735 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-09-06 [patent_title] => 'Microelectronic assembly formation with releasable leads' [patent_app_type] => utility [patent_app_number] => 10/235102 [patent_app_country] => US [patent_app_date] => 2002-09-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 25 [patent_no_of_words] => 8877 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/939/06939735.pdf [firstpage_image] =>[orig_patent_app_number] => 10235102 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/235102
Microelectronic assembly formation with releasable leads Sep 4, 2002 Issued
Array ( [id] => 996891 [patent_doc_number] => 06914333 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-05 [patent_title] => 'Wafer level package incorporating dual compliant layers and method for fabrication' [patent_app_type] => utility [patent_app_number] => 10/233802 [patent_app_country] => US [patent_app_date] => 2002-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 12 [patent_no_of_words] => 5431 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/914/06914333.pdf [firstpage_image] =>[orig_patent_app_number] => 10233802 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/233802
Wafer level package incorporating dual compliant layers and method for fabrication Sep 2, 2002 Issued
Array ( [id] => 7135126 [patent_doc_number] => 20040043571 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-03-04 [patent_title] => 'Buried-channel transistor with reduced leakage current' [patent_app_type] => new [patent_app_number] => 10/232586 [patent_app_country] => US [patent_app_date] => 2002-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5156 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0043/20040043571.pdf [firstpage_image] =>[orig_patent_app_number] => 10232586 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/232586
Buried-channel transistor with reduced leakage current Aug 29, 2002 Issued
Array ( [id] => 7394770 [patent_doc_number] => 20040038442 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-26 [patent_title] => 'Optically interactive device packages and methods of assembly' [patent_app_type] => new [patent_app_number] => 10/228411 [patent_app_country] => US [patent_app_date] => 2002-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 4889 [patent_no_of_claims] => 57 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0038/20040038442.pdf [firstpage_image] =>[orig_patent_app_number] => 10228411 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/228411
Optically interactive device packages and methods of assembly Aug 25, 2002 Abandoned
Array ( [id] => 6843244 [patent_doc_number] => 20030148591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-08-07 [patent_title] => 'Method of forming semiconductor device' [patent_app_type] => new [patent_app_number] => 10/226572 [patent_app_country] => US [patent_app_date] => 2002-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1391 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0148/20030148591.pdf [firstpage_image] =>[orig_patent_app_number] => 10226572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/226572
Method of forming semiconductor device Aug 22, 2002 Abandoned
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