
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1136280
[patent_doc_number] => 06784472
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-31
[patent_title] => 'Semiconductor device and method for fabricating the same'
[patent_app_type] => B2
[patent_app_number] => 10/219281
[patent_app_country] => US
[patent_app_date] => 2002-08-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 28
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[pdf_file] => patents/06/784/06784472.pdf
[firstpage_image] =>[orig_patent_app_number] => 10219281
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/219281 | Semiconductor device and method for fabricating the same | Aug 15, 2002 | Issued |
Array
(
[id] => 1141461
[patent_doc_number] => 06777297
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[patent_kind] => B2
[patent_issue_date] => 2004-08-17
[patent_title] => 'Disposable spacer and method of forming and using same'
[patent_app_type] => B2
[patent_app_number] => 10/218825
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[patent_app_date] => 2002-08-14
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[pdf_file] => patents/06/777/06777297.pdf
[firstpage_image] =>[orig_patent_app_number] => 10218825
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/218825 | Disposable spacer and method of forming and using same | Aug 13, 2002 | Issued |
Array
(
[id] => 6745266
[patent_doc_number] => 20030022449
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-01-30
[patent_title] => 'Method of manufacturing a semiconductor device having a trench isolation structure'
[patent_app_type] => new
[patent_app_number] => 10/212701
[patent_app_country] => US
[patent_app_date] => 2002-08-07
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[pdf_file] => publications/A1/0022/20030022449.pdf
[firstpage_image] =>[orig_patent_app_number] => 10212701
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/212701 | Method of manufacturing a semiconductor device having a trench isolation structure | Aug 6, 2002 | Abandoned |
Array
(
[id] => 7400611
[patent_doc_number] => 20040023461
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[patent_kind] => A1
[patent_issue_date] => 2004-02-05
[patent_title] => 'Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics'
[patent_app_type] => new
[patent_app_number] => 10/209581
[patent_app_country] => US
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/209581 | Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics | Jul 29, 2002 | Issued |
Array
(
[id] => 1196664
[patent_doc_number] => 06727150
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[patent_issue_date] => 2004-04-27
[patent_title] => 'Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers'
[patent_app_type] => B2
[patent_app_number] => 10/206171
[patent_app_country] => US
[patent_app_date] => 2002-07-26
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/206171 | Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers | Jul 25, 2002 | Issued |
Array
(
[id] => 8749377
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[patent_issue_date] => 2013-04-09
[patent_title] => 'Semiconductor device and peeling off method and method of manufacturing semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 10/193912
[patent_app_country] => US
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10193912
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/193912 | Semiconductor device and peeling off method and method of manufacturing semiconductor device | Jul 14, 2002 | Issued |
Array
(
[id] => 715504
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[patent_issue_date] => 2006-05-30
[patent_title] => 'Method for semiconductor wafer planarization by isolation material growth'
[patent_app_type] => utility
[patent_app_number] => 10/190002
[patent_app_country] => US
[patent_app_date] => 2002-07-03
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[firstpage_image] =>[orig_patent_app_number] => 10190002
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/190002 | Method for semiconductor wafer planarization by isolation material growth | Jul 2, 2002 | Issued |
Array
(
[id] => 1138262
[patent_doc_number] => 06780720
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-24
[patent_title] => 'Method for fabricating a nitrided silicon-oxide gate dielectric'
[patent_app_type] => B2
[patent_app_number] => 10/187572
[patent_app_country] => US
[patent_app_date] => 2002-07-01
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[pdf_file] => patents/06/780/06780720.pdf
[firstpage_image] =>[orig_patent_app_number] => 10187572
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/187572 | Method for fabricating a nitrided silicon-oxide gate dielectric | Jun 30, 2002 | Issued |
Array
(
[id] => 1212722
[patent_doc_number] => 06709931
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-03-23
[patent_title] => 'Fabrication of semiconductor devices having high-voltage MOS transistors and low-voltage MOS transistors'
[patent_app_type] => B2
[patent_app_number] => 10/184791
[patent_app_country] => US
[patent_app_date] => 2002-06-28
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[firstpage_image] =>[orig_patent_app_number] => 10184791
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/184791 | Fabrication of semiconductor devices having high-voltage MOS transistors and low-voltage MOS transistors | Jun 27, 2002 | Issued |
Array
(
[id] => 1009330
[patent_doc_number] => 06900092
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Surface engineering to prevent epi growth on gate poly during selective epi processing'
[patent_app_type] => utility
[patent_app_number] => 10/183336
[patent_app_country] => US
[patent_app_date] => 2002-06-27
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[firstpage_image] =>[orig_patent_app_number] => 10183336
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/183336 | Surface engineering to prevent epi growth on gate poly during selective epi processing | Jun 26, 2002 | Issued |
Array
(
[id] => 7433525
[patent_doc_number] => 20040002198
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[patent_issue_date] => 2004-01-01
[patent_title] => 'Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities'
[patent_app_type] => new
[patent_app_number] => 10/185192
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/185192 | Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities | Jun 26, 2002 | Issued |
Array
(
[id] => 1366349
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[patent_title] => 'Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step'
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Array
(
[id] => 993605
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[patent_title] => 'Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/167800 | Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor | Jun 11, 2002 | Issued |
Array
(
[id] => 1031051
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[patent_title] => 'Process for manufacturing a DMOS transistor'
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Array
(
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Array
(
[id] => 7625628
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[patent_title] => 'Method of producing semiconductor device and semiconductor substrate'
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Array
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/157192 | Hard mask etch for gate polyetch | May 29, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/311312 | Semiconductor device and its manufacturing method | May 7, 2002 | Issued |
Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/140441 | Transistors with controllable threshold voltages, and various methods of making and operating same | May 5, 2002 | Issued |