Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1136280 [patent_doc_number] => 06784472 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-31 [patent_title] => 'Semiconductor device and method for fabricating the same' [patent_app_type] => B2 [patent_app_number] => 10/219281 [patent_app_country] => US [patent_app_date] => 2002-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 69 [patent_no_of_words] => 7694 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/784/06784472.pdf [firstpage_image] =>[orig_patent_app_number] => 10219281 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/219281
Semiconductor device and method for fabricating the same Aug 15, 2002 Issued
Array ( [id] => 1141461 [patent_doc_number] => 06777297 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-17 [patent_title] => 'Disposable spacer and method of forming and using same' [patent_app_type] => B2 [patent_app_number] => 10/218825 [patent_app_country] => US [patent_app_date] => 2002-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 24 [patent_no_of_words] => 5502 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/777/06777297.pdf [firstpage_image] =>[orig_patent_app_number] => 10218825 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/218825
Disposable spacer and method of forming and using same Aug 13, 2002 Issued
Array ( [id] => 6745266 [patent_doc_number] => 20030022449 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-30 [patent_title] => 'Method of manufacturing a semiconductor device having a trench isolation structure' [patent_app_type] => new [patent_app_number] => 10/212701 [patent_app_country] => US [patent_app_date] => 2002-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20030022449.pdf [firstpage_image] =>[orig_patent_app_number] => 10212701 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/212701
Method of manufacturing a semiconductor device having a trench isolation structure Aug 6, 2002 Abandoned
Array ( [id] => 7400611 [patent_doc_number] => 20040023461 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-02-05 [patent_title] => 'Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics' [patent_app_type] => new [patent_app_number] => 10/209581 [patent_app_country] => US [patent_app_date] => 2002-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13465 [patent_no_of_claims] => 73 [patent_no_of_ind_claims] => 15 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0023/20040023461.pdf [firstpage_image] =>[orig_patent_app_number] => 10209581 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/209581
Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics Jul 29, 2002 Issued
Array ( [id] => 1196664 [patent_doc_number] => 06727150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-27 [patent_title] => 'Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers' [patent_app_type] => B2 [patent_app_number] => 10/206171 [patent_app_country] => US [patent_app_date] => 2002-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2429 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727150.pdf [firstpage_image] =>[orig_patent_app_number] => 10206171 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/206171
Methods of forming trench isolation within a semiconductor substrate including, Tshaped trench with spacers Jul 25, 2002 Issued
Array ( [id] => 8749377 [patent_doc_number] => 08415208 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Semiconductor device and peeling off method and method of manufacturing semiconductor device' [patent_app_type] => utility [patent_app_number] => 10/193912 [patent_app_country] => US [patent_app_date] => 2002-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 60 [patent_no_of_words] => 24978 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 10193912 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/193912
Semiconductor device and peeling off method and method of manufacturing semiconductor device Jul 14, 2002 Issued
Array ( [id] => 715504 [patent_doc_number] => 07052969 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2006-05-30 [patent_title] => 'Method for semiconductor wafer planarization by isolation material growth' [patent_app_type] => utility [patent_app_number] => 10/190002 [patent_app_country] => US [patent_app_date] => 2002-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 2374 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/052/07052969.pdf [firstpage_image] =>[orig_patent_app_number] => 10190002 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/190002
Method for semiconductor wafer planarization by isolation material growth Jul 2, 2002 Issued
Array ( [id] => 1138262 [patent_doc_number] => 06780720 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-08-24 [patent_title] => 'Method for fabricating a nitrided silicon-oxide gate dielectric' [patent_app_type] => B2 [patent_app_number] => 10/187572 [patent_app_country] => US [patent_app_date] => 2002-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3740 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/780/06780720.pdf [firstpage_image] =>[orig_patent_app_number] => 10187572 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/187572
Method for fabricating a nitrided silicon-oxide gate dielectric Jun 30, 2002 Issued
Array ( [id] => 1212722 [patent_doc_number] => 06709931 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-23 [patent_title] => 'Fabrication of semiconductor devices having high-voltage MOS transistors and low-voltage MOS transistors' [patent_app_type] => B2 [patent_app_number] => 10/184791 [patent_app_country] => US [patent_app_date] => 2002-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 3519 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/709/06709931.pdf [firstpage_image] =>[orig_patent_app_number] => 10184791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/184791
Fabrication of semiconductor devices having high-voltage MOS transistors and low-voltage MOS transistors Jun 27, 2002 Issued
Array ( [id] => 1009330 [patent_doc_number] => 06900092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Surface engineering to prevent epi growth on gate poly during selective epi processing' [patent_app_type] => utility [patent_app_number] => 10/183336 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3924 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900092.pdf [firstpage_image] =>[orig_patent_app_number] => 10183336 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/183336
Surface engineering to prevent epi growth on gate poly during selective epi processing Jun 26, 2002 Issued
Array ( [id] => 7433525 [patent_doc_number] => 20040002198 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2004-01-01 [patent_title] => 'Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities' [patent_app_type] => new [patent_app_number] => 10/185192 [patent_app_country] => US [patent_app_date] => 2002-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2273 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0002/20040002198.pdf [firstpage_image] =>[orig_patent_app_number] => 10185192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/185192
Seal ring and die corner stress relief pattern design to protect against moisture and metallic impurities Jun 26, 2002 Issued
Array ( [id] => 1366349 [patent_doc_number] => 06566150 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-05-20 [patent_title] => 'Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step' [patent_app_type] => B2 [patent_app_number] => 10/171695 [patent_app_country] => US [patent_app_date] => 2002-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9067 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/566/06566150.pdf [firstpage_image] =>[orig_patent_app_number] => 10171695 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/171695
Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step Jun 16, 2002 Issued
Array ( [id] => 993605 [patent_doc_number] => 06916704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-07-12 [patent_title] => 'Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor' [patent_app_type] => utility [patent_app_number] => 10/167800 [patent_app_country] => US [patent_app_date] => 2002-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 3723 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/916/06916704.pdf [firstpage_image] =>[orig_patent_app_number] => 10167800 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167800
Multiple deposition of metal layers for the fabrication of an upper capacitor electrode of a trench capacitor Jun 11, 2002 Issued
Array ( [id] => 1031051 [patent_doc_number] => 06878603 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-12 [patent_title] => 'Process for manufacturing a DMOS transistor' [patent_app_type] => utility [patent_app_number] => 10/167961 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4091 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/878/06878603.pdf [firstpage_image] =>[orig_patent_app_number] => 10167961 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167961
Process for manufacturing a DMOS transistor Jun 10, 2002 Issued
Array ( [id] => 6755861 [patent_doc_number] => 20030003638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-02 [patent_title] => 'Process for manufacturing a DMOS transistor' [patent_app_type] => new [patent_app_number] => 10/167960 [patent_app_country] => US [patent_app_date] => 2002-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4332 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0003/20030003638.pdf [firstpage_image] =>[orig_patent_app_number] => 10167960 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/167960
Process for manufacturing a DMOS transistor Jun 10, 2002 Issued
Array ( [id] => 7625628 [patent_doc_number] => 06723541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-20 [patent_title] => 'Method of producing semiconductor device and semiconductor substrate' [patent_app_type] => B2 [patent_app_number] => 10/163312 [patent_app_country] => US [patent_app_date] => 2002-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 8575 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 16 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/723/06723541.pdf [firstpage_image] =>[orig_patent_app_number] => 10163312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/163312
Method of producing semiconductor device and semiconductor substrate Jun 6, 2002 Issued
Array ( [id] => 6635817 [patent_doc_number] => 20030006492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-01-09 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => new [patent_app_number] => 10/157823 [patent_app_country] => US [patent_app_date] => 2002-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 9415 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20030006492.pdf [firstpage_image] =>[orig_patent_app_number] => 10157823 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157823
Semiconductor device and method of manufacturing the same May 30, 2002 Abandoned
Array ( [id] => 544071 [patent_doc_number] => 07163879 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-01-16 [patent_title] => 'Hard mask etch for gate polyetch' [patent_app_type] => utility [patent_app_number] => 10/157192 [patent_app_country] => US [patent_app_date] => 2002-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 3269 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/163/07163879.pdf [firstpage_image] =>[orig_patent_app_number] => 10157192 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/157192
Hard mask etch for gate polyetch May 29, 2002 Issued
Array ( [id] => 637802 [patent_doc_number] => 07125754 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-10-24 [patent_title] => 'Semiconductor device and its manufacturing method' [patent_app_type] => utility [patent_app_number] => 10/311312 [patent_app_country] => US [patent_app_date] => 2002-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 26 [patent_no_of_words] => 15581 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/125/07125754.pdf [firstpage_image] =>[orig_patent_app_number] => 10311312 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/311312
Semiconductor device and its manufacturing method May 7, 2002 Issued
Array ( [id] => 6725192 [patent_doc_number] => 20030207504 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Transistors with controllable threshold voltages, and various methods of making and operating same' [patent_app_type] => new [patent_app_number] => 10/140441 [patent_app_country] => US [patent_app_date] => 2002-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10650 [patent_no_of_claims] => 63 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207504.pdf [firstpage_image] =>[orig_patent_app_number] => 10140441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/140441
Transistors with controllable threshold voltages, and various methods of making and operating same May 5, 2002 Issued
Menu