
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 732633
[patent_doc_number] => 07037791
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-05-02
[patent_title] => 'Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates'
[patent_app_type] => utility
[patent_app_number] => 10/135071
[patent_app_country] => US
[patent_app_date] => 2002-04-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/037/07037791.pdf
[firstpage_image] =>[orig_patent_app_number] => 10135071
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/135071 | Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates | Apr 29, 2002 | Issued |
Array
(
[id] => 6761446
[patent_doc_number] => 20030124808
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-03
[patent_title] => 'SYSTEM FOR REDUCING SILICON-CONSUMPTION THROUGH SELECTIVE DEPOSITION'
[patent_app_type] => new
[patent_app_number] => 10/131162
[patent_app_country] => US
[patent_app_date] => 2002-04-24
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0124/20030124808.pdf
[firstpage_image] =>[orig_patent_app_number] => 10131162
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/131162 | System for reducing silicon-consumption through selective deposition | Apr 23, 2002 | Issued |
Array
(
[id] => 6158064
[patent_doc_number] => 20020146891
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-10-10
[patent_title] => 'Method for forming isolation trench'
[patent_app_type] => new
[patent_app_number] => 10/118671
[patent_app_country] => US
[patent_app_date] => 2002-04-08
[patent_effective_date] => 0000-00-00
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[firstpage_image] =>[orig_patent_app_number] => 10118671
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/118671 | Method for forming isolation trench | Apr 7, 2002 | Issued |
Array
(
[id] => 658033
[patent_doc_number] => 07105360
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-09-12
[patent_title] => 'Low temperature melt-processing of organic-inorganic hybrid'
[patent_app_type] => utility
[patent_app_number] => 10/094351
[patent_app_country] => US
[patent_app_date] => 2002-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
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[patent_no_of_words] => 9881
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[firstpage_image] =>[orig_patent_app_number] => 10094351
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/094351 | Low temperature melt-processing of organic-inorganic hybrid | Mar 7, 2002 | Issued |
Array
(
[id] => 1245699
[patent_doc_number] => 06677210
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-01-13
[patent_title] => 'High voltage transistors with graded extension'
[patent_app_type] => B1
[patent_app_number] => 10/087881
[patent_app_country] => US
[patent_app_date] => 2002-02-28
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[firstpage_image] =>[orig_patent_app_number] => 10087881
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/087881 | High voltage transistors with graded extension | Feb 27, 2002 | Issued |
Array
(
[id] => 1005344
[patent_doc_number] => 06905939
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-06-14
[patent_title] => 'Process for forming silicon oxide material'
[patent_app_type] => utility
[patent_app_number] => 10/090103
[patent_app_country] => US
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[pdf_file] => patents/06/905/06905939.pdf
[firstpage_image] =>[orig_patent_app_number] => 10090103
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/090103 | Process for forming silicon oxide material | Feb 26, 2002 | Issued |
Array
(
[id] => 1009719
[patent_doc_number] => 06900481
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[patent_kind] => B2
[patent_issue_date] => 2005-05-31
[patent_title] => 'Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors'
[patent_app_type] => utility
[patent_app_number] => 10/081992
[patent_app_country] => US
[patent_app_date] => 2002-02-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
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[patent_no_of_words] => 3397
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[pdf_file] => patents/06/900/06900481.pdf
[firstpage_image] =>[orig_patent_app_number] => 10081992
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/081992 | Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors | Feb 20, 2002 | Issued |
Array
(
[id] => 744709
[patent_doc_number] => 07026219
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2006-04-11
[patent_title] => 'Integration of high k gate dielectric'
[patent_app_type] => utility
[patent_app_number] => 10/074722
[patent_app_country] => US
[patent_app_date] => 2002-02-11
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/026/07026219.pdf
[firstpage_image] =>[orig_patent_app_number] => 10074722
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/074722 | Integration of high k gate dielectric | Feb 10, 2002 | Issued |
Array
(
[id] => 1205544
[patent_doc_number] => 06716712
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-04-06
[patent_title] => 'Process for producing two differently doped adjacent regions in an integrated semiconductor'
[patent_app_type] => B2
[patent_app_number] => 10/054441
[patent_app_country] => US
[patent_app_date] => 2002-01-22
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[pdf_file] => patents/06/716/06716712.pdf
[firstpage_image] =>[orig_patent_app_number] => 10054441
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/054441 | Process for producing two differently doped adjacent regions in an integrated semiconductor | Jan 21, 2002 | Issued |
Array
(
[id] => 5828666
[patent_doc_number] => 20020068377
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-06-06
[patent_title] => 'Method of forming a film of a semiconductor device'
[patent_app_type] => new
[patent_app_number] => 10/050911
[patent_app_country] => US
[patent_app_date] => 2002-01-22
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[pdf_file] => publications/A1/0068/20020068377.pdf
[firstpage_image] =>[orig_patent_app_number] => 10050911
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/050911 | Method of forming a film of a semiconductor device | Jan 21, 2002 | Abandoned |
Array
(
[id] => 6659696
[patent_doc_number] => 20030134479
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2003-07-17
[patent_title] => 'Eliminating substrate noise by an electrically isolated high-voltage I/O transistor'
[patent_app_type] => new
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[pdf_file] => publications/A1/0134/20030134479.pdf
[firstpage_image] =>[orig_patent_app_number] => 10051962
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/051962 | Eliminating substrate noise by an electrically isolated high-voltage I/O transistor | Jan 15, 2002 | Abandoned |
Array
(
[id] => 6761387
[patent_doc_number] => 20030124749
[patent_country] => US
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[patent_issue_date] => 2003-07-03
[patent_title] => 'Method for inspecting a pattern defect process'
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[firstpage_image] =>[orig_patent_app_number] => 10038691
[rel_patent_id] =>[rel_patent_doc_number] =>) 10/038691 | Method for inspecting a pattern defect process | Jan 1, 2002 | Issued |
Array
(
[id] => 1500379
[patent_doc_number] => 06486048
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[patent_kind] => B1
[patent_issue_date] => 2002-11-26
[patent_title] => 'Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source drain'
[patent_app_type] => B1
[patent_app_number] => 10/034791
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/034791 | Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source drain | Dec 26, 2001 | Issued |
Array
(
[id] => 1210799
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[patent_title] => 'Process using poly-buffered STI'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/029512 | Process using poly-buffered STI | Dec 20, 2001 | Issued |
Array
(
[id] => 1248264
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[patent_title] => 'Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/023982 | Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same | Dec 20, 2001 | Issued |
Array
(
[id] => 6668989
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[patent_title] => 'Method for fabricating local interconnects'
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[firstpage_image] =>[orig_patent_app_number] => 09683341
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/683341 | Method for fabricating local interconnects | Dec 16, 2001 | Abandoned |
Array
(
[id] => 1415499
[patent_doc_number] => 06518105
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[patent_title] => 'High performance PD SOI tunneling-biased MOSFET'
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[patent_app_number] => 10/021702
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/021702 | High performance PD SOI tunneling-biased MOSFET | Dec 9, 2001 | Issued |
Array
(
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[patent_title] => 'Method of manufacturing a semiconductor device including forming well comprising EPI in trench'
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Array
(
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[rel_patent_id] =>[rel_patent_doc_number] =>) 10/010162 | Method of forming narrow trenches in semiconductor substrates | Nov 19, 2001 | Issued |
Array
(
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[patent_title] => 'Lightly-insitu-doped amorphous silicon applied in DRAM gates'
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[firstpage_image] =>[orig_patent_app_number] => 09986741
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/986741 | Lightly-insitu-doped amorphous silicon applied in DRAM gates | Nov 8, 2001 | Abandoned |