Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 732633 [patent_doc_number] => 07037791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-05-02 [patent_title] => 'Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates' [patent_app_type] => utility [patent_app_number] => 10/135071 [patent_app_country] => US [patent_app_date] => 2002-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 23 [patent_no_of_words] => 4553 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/037/07037791.pdf [firstpage_image] =>[orig_patent_app_number] => 10135071 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/135071
Application of single exposure alternating aperture phase shift mask to form sub 0.18 micron polysilicon gates Apr 29, 2002 Issued
Array ( [id] => 6761446 [patent_doc_number] => 20030124808 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'SYSTEM FOR REDUCING SILICON-CONSUMPTION THROUGH SELECTIVE DEPOSITION' [patent_app_type] => new [patent_app_number] => 10/131162 [patent_app_country] => US [patent_app_date] => 2002-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2866 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 45 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124808.pdf [firstpage_image] =>[orig_patent_app_number] => 10131162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/131162
System for reducing silicon-consumption through selective deposition Apr 23, 2002 Issued
Array ( [id] => 6158064 [patent_doc_number] => 20020146891 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-10 [patent_title] => 'Method for forming isolation trench' [patent_app_type] => new [patent_app_number] => 10/118671 [patent_app_country] => US [patent_app_date] => 2002-04-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3774 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 37 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20020146891.pdf [firstpage_image] =>[orig_patent_app_number] => 10118671 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/118671
Method for forming isolation trench Apr 7, 2002 Issued
Array ( [id] => 658033 [patent_doc_number] => 07105360 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-09-12 [patent_title] => 'Low temperature melt-processing of organic-inorganic hybrid' [patent_app_type] => utility [patent_app_number] => 10/094351 [patent_app_country] => US [patent_app_date] => 2002-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9881 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/105/07105360.pdf [firstpage_image] =>[orig_patent_app_number] => 10094351 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/094351
Low temperature melt-processing of organic-inorganic hybrid Mar 7, 2002 Issued
Array ( [id] => 1245699 [patent_doc_number] => 06677210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'High voltage transistors with graded extension' [patent_app_type] => B1 [patent_app_number] => 10/087881 [patent_app_country] => US [patent_app_date] => 2002-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 31 [patent_no_of_words] => 9389 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677210.pdf [firstpage_image] =>[orig_patent_app_number] => 10087881 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/087881
High voltage transistors with graded extension Feb 27, 2002 Issued
Array ( [id] => 1005344 [patent_doc_number] => 06905939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-06-14 [patent_title] => 'Process for forming silicon oxide material' [patent_app_type] => utility [patent_app_number] => 10/090103 [patent_app_country] => US [patent_app_date] => 2002-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2807 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/905/06905939.pdf [firstpage_image] =>[orig_patent_app_number] => 10090103 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/090103
Process for forming silicon oxide material Feb 26, 2002 Issued
Array ( [id] => 1009719 [patent_doc_number] => 06900481 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-05-31 [patent_title] => 'Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors' [patent_app_type] => utility [patent_app_number] => 10/081992 [patent_app_country] => US [patent_app_date] => 2002-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3397 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/900/06900481.pdf [firstpage_image] =>[orig_patent_app_number] => 10081992 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/081992
Non-silicon semiconductor and high-k gate dielectric metal oxide semiconductor field effect transistors Feb 20, 2002 Issued
Array ( [id] => 744709 [patent_doc_number] => 07026219 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2006-04-11 [patent_title] => 'Integration of high k gate dielectric' [patent_app_type] => utility [patent_app_number] => 10/074722 [patent_app_country] => US [patent_app_date] => 2002-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 9249 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/026/07026219.pdf [firstpage_image] =>[orig_patent_app_number] => 10074722 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/074722
Integration of high k gate dielectric Feb 10, 2002 Issued
Array ( [id] => 1205544 [patent_doc_number] => 06716712 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-04-06 [patent_title] => 'Process for producing two differently doped adjacent regions in an integrated semiconductor' [patent_app_type] => B2 [patent_app_number] => 10/054441 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 4266 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/716/06716712.pdf [firstpage_image] =>[orig_patent_app_number] => 10054441 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/054441
Process for producing two differently doped adjacent regions in an integrated semiconductor Jan 21, 2002 Issued
Array ( [id] => 5828666 [patent_doc_number] => 20020068377 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-06 [patent_title] => 'Method of forming a film of a semiconductor device' [patent_app_type] => new [patent_app_number] => 10/050911 [patent_app_country] => US [patent_app_date] => 2002-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3513 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0068/20020068377.pdf [firstpage_image] =>[orig_patent_app_number] => 10050911 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/050911
Method of forming a film of a semiconductor device Jan 21, 2002 Abandoned
Array ( [id] => 6659696 [patent_doc_number] => 20030134479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-17 [patent_title] => 'Eliminating substrate noise by an electrically isolated high-voltage I/O transistor' [patent_app_type] => new [patent_app_number] => 10/051962 [patent_app_country] => US [patent_app_date] => 2002-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4780 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20030134479.pdf [firstpage_image] =>[orig_patent_app_number] => 10051962 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/051962
Eliminating substrate noise by an electrically isolated high-voltage I/O transistor Jan 15, 2002 Abandoned
Array ( [id] => 6761387 [patent_doc_number] => 20030124749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-07-03 [patent_title] => 'Method for inspecting a pattern defect process' [patent_app_type] => new [patent_app_number] => 10/038691 [patent_app_country] => US [patent_app_date] => 2002-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1502 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20030124749.pdf [firstpage_image] =>[orig_patent_app_number] => 10038691 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/038691
Method for inspecting a pattern defect process Jan 1, 2002 Issued
Array ( [id] => 1500379 [patent_doc_number] => 06486048 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-26 [patent_title] => 'Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source drain' [patent_app_type] => B1 [patent_app_number] => 10/034791 [patent_app_country] => US [patent_app_date] => 2001-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 1585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486048.pdf [firstpage_image] =>[orig_patent_app_number] => 10034791 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/034791
Method for fabricating a semiconductor device using conductive oxide and metal layer to silicide source drain Dec 26, 2001 Issued
Array ( [id] => 1210799 [patent_doc_number] => 06713780 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-03-30 [patent_title] => 'Process using poly-buffered STI' [patent_app_type] => B2 [patent_app_number] => 10/029512 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 2783 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713780.pdf [firstpage_image] =>[orig_patent_app_number] => 10029512 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/029512
Process using poly-buffered STI Dec 20, 2001 Issued
Array ( [id] => 1248264 [patent_doc_number] => 06673706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-01-06 [patent_title] => 'Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same' [patent_app_type] => B2 [patent_app_number] => 10/023982 [patent_app_country] => US [patent_app_date] => 2001-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 37 [patent_no_of_words] => 6087 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 299 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/673/06673706.pdf [firstpage_image] =>[orig_patent_app_number] => 10023982 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/023982
Method of forming a pattern using a photoresist without exposing the photoresist and silicidation method incorporating the same Dec 20, 2001 Issued
Array ( [id] => 6668989 [patent_doc_number] => 20030113973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-06-19 [patent_title] => 'Method for fabricating local interconnects' [patent_app_type] => new [patent_app_number] => 09/683341 [patent_app_country] => US [patent_app_date] => 2001-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 1979 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20030113973.pdf [firstpage_image] =>[orig_patent_app_number] => 09683341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/683341
Method for fabricating local interconnects Dec 16, 2001 Abandoned
Array ( [id] => 1415499 [patent_doc_number] => 06518105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'High performance PD SOI tunneling-biased MOSFET' [patent_app_type] => B1 [patent_app_number] => 10/021702 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 1563 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518105.pdf [firstpage_image] =>[orig_patent_app_number] => 10021702 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/021702
High performance PD SOI tunneling-biased MOSFET Dec 9, 2001 Issued
Array ( [id] => 1588863 [patent_doc_number] => 06482717 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method of manufacturing a semiconductor device including forming well comprising EPI in trench' [patent_app_type] => B1 [patent_app_number] => 10/016762 [patent_app_country] => US [patent_app_date] => 2001-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2790 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/482/06482717.pdf [firstpage_image] =>[orig_patent_app_number] => 10016762 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/016762
Method of manufacturing a semiconductor device including forming well comprising EPI in trench Dec 9, 2001 Issued
Array ( [id] => 6801314 [patent_doc_number] => 20030096479 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-22 [patent_title] => 'Method of forming narrow trenches in semiconductor substrates' [patent_app_type] => new [patent_app_number] => 10/010162 [patent_app_country] => US [patent_app_date] => 2001-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3149 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20030096479.pdf [firstpage_image] =>[orig_patent_app_number] => 10010162 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/010162
Method of forming narrow trenches in semiconductor substrates Nov 19, 2001 Issued
Array ( [id] => 6861241 [patent_doc_number] => 20030092249 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-05-15 [patent_title] => 'Lightly-insitu-doped amorphous silicon applied in DRAM gates' [patent_app_type] => new [patent_app_number] => 09/986741 [patent_app_country] => US [patent_app_date] => 2001-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2564 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0092/20030092249.pdf [firstpage_image] =>[orig_patent_app_number] => 09986741 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986741
Lightly-insitu-doped amorphous silicon applied in DRAM gates Nov 8, 2001 Abandoned
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