Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1424144 [patent_doc_number] => 06515320 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-04 [patent_title] => 'Semiconductor device and method of manufacturing the same including thicker insulating layer on lower part of electrode' [patent_app_type] => B1 [patent_app_number] => 09/986362 [patent_app_country] => US [patent_app_date] => 2001-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 3471 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/515/06515320.pdf [firstpage_image] =>[orig_patent_app_number] => 09986362 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/986362
Semiconductor device and method of manufacturing the same including thicker insulating layer on lower part of electrode Nov 7, 2001 Issued
Array ( [id] => 5874060 [patent_doc_number] => 20020048885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-25 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => new [patent_app_number] => 09/985881 [patent_app_country] => US [patent_app_date] => 2001-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8612 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0048/20020048885.pdf [firstpage_image] =>[orig_patent_app_number] => 09985881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/985881
Method for fabricating semiconductor device Nov 5, 2001 Issued
Array ( [id] => 229220 [patent_doc_number] => 07602035 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-10-13 [patent_title] => 'Light emitting or light receiving semiconductor module and method for manufacturing same' [patent_app_type] => utility [patent_app_number] => 10/492561 [patent_app_country] => US [patent_app_date] => 2001-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 26 [patent_no_of_words] => 10235 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 520 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/602/07602035.pdf [firstpage_image] =>[orig_patent_app_number] => 10492561 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/492561
Light emitting or light receiving semiconductor module and method for manufacturing same Oct 18, 2001 Issued
Array ( [id] => 6657228 [patent_doc_number] => 20030077877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-04-24 [patent_title] => 'Systems and methods for electrically isolating portions of wafers' [patent_app_type] => new [patent_app_number] => 10/035792 [patent_app_country] => US [patent_app_date] => 2001-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2271 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0077/20030077877.pdf [firstpage_image] =>[orig_patent_app_number] => 10035792 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/035792
Systems and methods for electrically isolating portions of wafers Oct 17, 2001 Issued
Array ( [id] => 6444640 [patent_doc_number] => 20020149068 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-17 [patent_title] => 'Method of manufacturing semiconductor device, and semiconductor device having memory cell' [patent_app_type] => new [patent_app_number] => 09/976341 [patent_app_country] => US [patent_app_date] => 2001-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9558 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0149/20020149068.pdf [firstpage_image] =>[orig_patent_app_number] => 09976341 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/976341
Method of manufacturing semiconductor device, and semiconductor device having memory cell Oct 14, 2001 Issued
Array ( [id] => 1595418 [patent_doc_number] => 06492212 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Variable threshold voltage double gated transistors and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/972172 [patent_app_country] => US [patent_app_date] => 2001-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 7120 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492212.pdf [firstpage_image] =>[orig_patent_app_number] => 09972172 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/972172
Variable threshold voltage double gated transistors and method of fabrication Oct 4, 2001 Issued
Array ( [id] => 7623561 [patent_doc_number] => 06686604 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-02-03 [patent_title] => 'Multiple operating voltage vertical replacement-gate (VRG) transistor' [patent_app_type] => B2 [patent_app_number] => 09/961477 [patent_app_country] => US [patent_app_date] => 2001-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 6567 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/686/06686604.pdf [firstpage_image] =>[orig_patent_app_number] => 09961477 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/961477
Multiple operating voltage vertical replacement-gate (VRG) transistor Sep 20, 2001 Issued
Array ( [id] => 6406001 [patent_doc_number] => 20020037639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Method for farbricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type' [patent_app_type] => new [patent_app_number] => 09/951241 [patent_app_country] => US [patent_app_date] => 2001-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2441 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037639.pdf [firstpage_image] =>[orig_patent_app_number] => 09951241 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/951241
Method for fabricating field-effect transistors in integrated semiconductor circuits and integrated semiconductor circuit fabricated with a field-effect transistor of this type including a dual gate Sep 11, 2001 Issued
Array ( [id] => 1440063 [patent_doc_number] => 06495431 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-17 [patent_title] => 'Semiconductor device and method for manufacturing the same that includes a dual oxidation' [patent_app_type] => B2 [patent_app_number] => 09/919921 [patent_app_country] => US [patent_app_date] => 2001-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 60 [patent_no_of_words] => 13217 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/495/06495431.pdf [firstpage_image] =>[orig_patent_app_number] => 09919921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/919921
Semiconductor device and method for manufacturing the same that includes a dual oxidation Aug 1, 2001 Issued
Array ( [id] => 1040569 [patent_doc_number] => 06869867 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-03-22 [patent_title] => 'SEMICONDUCTOR DEVICE COMPRISING METAL SILICIDE FILMS FORMED TO COVER GATE ELECTRODE AND SOURCE-DRAIN DIFFUSION LAYERS AND METHOD OF MANUFACTURING THE SAME WHEREIN THE SILICIDE ON GATE IS THICKER THAN ON SOURCE-DRAIN' [patent_app_type] => utility [patent_app_number] => 09/916530 [patent_app_country] => US [patent_app_date] => 2001-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 32 [patent_no_of_words] => 13951 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/869/06869867.pdf [firstpage_image] =>[orig_patent_app_number] => 09916530 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/916530
SEMICONDUCTOR DEVICE COMPRISING METAL SILICIDE FILMS FORMED TO COVER GATE ELECTRODE AND SOURCE-DRAIN DIFFUSION LAYERS AND METHOD OF MANUFACTURING THE SAME WHEREIN THE SILICIDE ON GATE IS THICKER THAN ON SOURCE-DRAIN Jul 29, 2001 Issued
Array ( [id] => 6884946 [patent_doc_number] => 20010039108 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-08 [patent_title] => 'Method for forming gate' [patent_app_type] => new [patent_app_number] => 09/901211 [patent_app_country] => US [patent_app_date] => 2001-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2302 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 99 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0039/20010039108.pdf [firstpage_image] =>[orig_patent_app_number] => 09901211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/901211
Method for forming gate Jul 8, 2001 Abandoned
Array ( [id] => 1532522 [patent_doc_number] => 06410405 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge' [patent_app_type] => B1 [patent_app_number] => 09/895411 [patent_app_country] => US [patent_app_date] => 2001-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 1897 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410405.pdf [firstpage_image] =>[orig_patent_app_number] => 09895411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/895411
Method for forming a field oxide film on a semiconductor device including mask spacer and rounding edge Jul 1, 2001 Issued
Array ( [id] => 1414446 [patent_doc_number] => 06521509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-02-18 [patent_title] => 'Semiconductor device and method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/887322 [patent_app_country] => US [patent_app_date] => 2001-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 3126 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/521/06521509.pdf [firstpage_image] =>[orig_patent_app_number] => 09887322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/887322
Semiconductor device and method of manufacturing the same Jun 24, 2001 Issued
Array ( [id] => 6494218 [patent_doc_number] => 20020190318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-19 [patent_title] => 'Divot reduction in SIMOX layers' [patent_app_type] => new [patent_app_number] => 09/884670 [patent_app_country] => US [patent_app_date] => 2001-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5384 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0190/20020190318.pdf [firstpage_image] =>[orig_patent_app_number] => 09884670 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/884670
Divot reduction in SIMOX layers Jun 18, 2001 Abandoned
Array ( [id] => 1172945 [patent_doc_number] => 06750159 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-06-15 [patent_title] => 'Semiconductor apparatus, manufacturing method therefor, solid state image device and manufacturing method therefor' [patent_app_type] => B2 [patent_app_number] => 09/878841 [patent_app_country] => US [patent_app_date] => 2001-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 29 [patent_no_of_words] => 8359 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/750/06750159.pdf [firstpage_image] =>[orig_patent_app_number] => 09878841 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/878841
Semiconductor apparatus, manufacturing method therefor, solid state image device and manufacturing method therefor Jun 10, 2001 Issued
Array ( [id] => 6260606 [patent_doc_number] => 20020187615 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-12 [patent_title] => 'Method for forming isolations in memory devices with common source lines' [patent_app_type] => new [patent_app_number] => 09/875152 [patent_app_country] => US [patent_app_date] => 2001-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3461 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0187/20020187615.pdf [firstpage_image] =>[orig_patent_app_number] => 09875152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/875152
Method for forming isolations in memory devices with common source lines Jun 6, 2001 Abandoned
Array ( [id] => 6385304 [patent_doc_number] => 20020179997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-12-05 [patent_title] => 'Self-aligned corner Vt enhancement with isolation channel stop by ion implantation' [patent_app_type] => new [patent_app_number] => 09/874121 [patent_app_country] => US [patent_app_date] => 2001-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1213 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0179/20020179997.pdf [firstpage_image] =>[orig_patent_app_number] => 09874121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/874121
Self-aligned corner Vt enhancement with isolation channel stop by ion implantation Jun 4, 2001 Abandoned
Array ( [id] => 7000636 [patent_doc_number] => 20010053593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-20 [patent_title] => 'Method of forming metal oxide gate structures and capacitor electrodes' [patent_app_type] => new [patent_app_number] => 09/870631 [patent_app_country] => US [patent_app_date] => 2001-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2961 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20010053593.pdf [firstpage_image] =>[orig_patent_app_number] => 09870631 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/870631
Method of forming metal oxide gate structures and capacitor electrodes May 31, 2001 Pending
Array ( [id] => 6485511 [patent_doc_number] => 20020024621 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'Method of manufacturing liquid crystal display device' [patent_app_type] => new [patent_app_number] => 09/854120 [patent_app_country] => US [patent_app_date] => 2001-05-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 20184 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0024/20020024621.pdf [firstpage_image] =>[orig_patent_app_number] => 09854120 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/854120
Method of manufacturing liquid crystal display device May 9, 2001 Issued
Array ( [id] => 7629810 [patent_doc_number] => 06818546 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-16 [patent_title] => 'Semiconductor integrated circuit device and a method of manufacturing the same' [patent_app_type] => B2 [patent_app_number] => 09/850162 [patent_app_country] => US [patent_app_date] => 2001-05-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 55 [patent_no_of_words] => 14330 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818546.pdf [firstpage_image] =>[orig_patent_app_number] => 09850162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/850162
Semiconductor integrated circuit device and a method of manufacturing the same May 7, 2001 Issued
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