Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1316028 [patent_doc_number] => 06611023 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-26 [patent_title] => 'Field effect transistor with self alligned double gate and method of forming same' [patent_app_type] => B1 [patent_app_number] => 09/846502 [patent_app_country] => US [patent_app_date] => 2001-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 15 [patent_no_of_words] => 3941 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611023.pdf [firstpage_image] =>[orig_patent_app_number] => 09846502 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/846502
Field effect transistor with self alligned double gate and method of forming same Apr 30, 2001 Issued
Array ( [id] => 1175222 [patent_doc_number] => 06746926 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-08 [patent_title] => 'MOS transistor with highly localized super halo implant' [patent_app_type] => B1 [patent_app_number] => 09/844752 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1112 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/746/06746926.pdf [firstpage_image] =>[orig_patent_app_number] => 09844752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/844752
MOS transistor with highly localized super halo implant Apr 26, 2001 Issued
Array ( [id] => 1503481 [patent_doc_number] => 06465312 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'CMOS transistor with amorphous silicon elevated source-drain structure and method of fabrication' [patent_app_type] => B1 [patent_app_number] => 09/845602 [patent_app_country] => US [patent_app_date] => 2001-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 1995 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/465/06465312.pdf [firstpage_image] =>[orig_patent_app_number] => 09845602 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/845602
CMOS transistor with amorphous silicon elevated source-drain structure and method of fabrication Apr 26, 2001 Issued
Array ( [id] => 1578047 [patent_doc_number] => 06448120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Totally self-aligned transistor with tungsten gate' [patent_app_type] => B1 [patent_app_number] => 09/837152 [patent_app_country] => US [patent_app_date] => 2001-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2133 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 28 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/448/06448120.pdf [firstpage_image] =>[orig_patent_app_number] => 09837152 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/837152
Totally self-aligned transistor with tungsten gate Apr 16, 2001 Issued
Array ( [id] => 1043668 [patent_doc_number] => 06867101 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-03-15 [patent_title] => 'Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed' [patent_app_type] => utility [patent_app_number] => 09/826472 [patent_app_country] => US [patent_app_date] => 2001-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2112 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/867/06867101.pdf [firstpage_image] =>[orig_patent_app_number] => 09826472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/826472
Method of fabricating a semiconductor device having a nitride/high-k/nitride gate dielectric stack by atomic layer deposition (ALD) and a device thereby formed Apr 3, 2001 Issued
Array ( [id] => 1351802 [patent_doc_number] => 06580122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Transistor device having an enhanced width dimension and a method of making same' [patent_app_type] => B1 [patent_app_number] => 09/812521 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 4247 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/580/06580122.pdf [firstpage_image] =>[orig_patent_app_number] => 09812521 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/812521
Transistor device having an enhanced width dimension and a method of making same Mar 19, 2001 Issued
Array ( [id] => 1396739 [patent_doc_number] => 06531367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'Method for forming ultra-shallow junction by boron plasma doping' [patent_app_type] => B2 [patent_app_number] => 09/811472 [patent_app_country] => US [patent_app_date] => 2001-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1749 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531367.pdf [firstpage_image] =>[orig_patent_app_number] => 09811472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/811472
Method for forming ultra-shallow junction by boron plasma doping Mar 19, 2001 Issued
Array ( [id] => 6405845 [patent_doc_number] => 20020037619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-03-28 [patent_title] => 'Semiconductor device and method of producing the same' [patent_app_type] => new [patent_app_number] => 09/809211 [patent_app_country] => US [patent_app_date] => 2001-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9551 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0037/20020037619.pdf [firstpage_image] =>[orig_patent_app_number] => 09809211 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/809211
Semiconductor device Mar 15, 2001 Issued
Array ( [id] => 1500309 [patent_doc_number] => 06486030 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-26 [patent_title] => 'Methods of forming field effect transistors and integrated circuitry including TiN gate element' [patent_app_type] => B2 [patent_app_number] => 09/810752 [patent_app_country] => US [patent_app_date] => 2001-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 5128 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/486/06486030.pdf [firstpage_image] =>[orig_patent_app_number] => 09810752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/810752
Methods of forming field effect transistors and integrated circuitry including TiN gate element Mar 14, 2001 Issued
Array ( [id] => 5839800 [patent_doc_number] => 20020130102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-09-19 [patent_title] => 'Method of forming a thin-film resistor employed in a semiconductor water' [patent_app_type] => new [patent_app_number] => 09/803883 [patent_app_country] => US [patent_app_date] => 2001-03-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1630 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20020130102.pdf [firstpage_image] =>[orig_patent_app_number] => 09803883 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/803883
Method of forming a thin-film resistor employed in a semiconductor water Mar 12, 2001 Abandoned
Array ( [id] => 1253368 [patent_doc_number] => 06670263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-30 [patent_title] => 'Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size' [patent_app_type] => B2 [patent_app_number] => 09/802702 [patent_app_country] => US [patent_app_date] => 2001-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2356 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/670/06670263.pdf [firstpage_image] =>[orig_patent_app_number] => 09802702 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/802702
Method of reducing polysilicon depletion in a polysilicon gate electrode by depositing polysilicon of varying grain size Mar 9, 2001 Issued
Array ( [id] => 6827689 [patent_doc_number] => 20030178747 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-09-25 [patent_title] => 'Device for packing electronic components using injection moulding technology' [patent_app_type] => new [patent_app_number] => 10/220752 [patent_app_country] => US [patent_app_date] => 2002-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5372 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 32 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20030178747.pdf [firstpage_image] =>[orig_patent_app_number] => 10220752 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/220752
Device for packing electronic components using injection molding technology Mar 1, 2001 Issued
Array ( [id] => 7014536 [patent_doc_number] => 20010051396 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-12-13 [patent_title] => 'Method for fabricating electronic circuit device, semiconductor device and electronic circuit device' [patent_app_type] => new [patent_app_number] => 09/783021 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 9584 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0051/20010051396.pdf [firstpage_image] =>[orig_patent_app_number] => 09783021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783021
Method for fabricating electronic circuit device, semiconductor device and electronic circuit device including bump bonding Feb 14, 2001 Issued
Array ( [id] => 6547963 [patent_doc_number] => 20020110995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-08-15 [patent_title] => 'Use of discrete chemical mechanical polishing processes to form a trench isolation region' [patent_app_type] => new [patent_app_number] => 09/783042 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3107 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0110/20020110995.pdf [firstpage_image] =>[orig_patent_app_number] => 09783042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/783042
Use of discrete chemical mechanical polishing processes to form a trench isolation region Feb 14, 2001 Abandoned
Array ( [id] => 1034461 [patent_doc_number] => 06875670 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2005-04-05 [patent_title] => 'Trench isolation method' [patent_app_type] => utility [patent_app_number] => 09/775231 [patent_app_country] => US [patent_app_date] => 2001-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 2299 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/875/06875670.pdf [firstpage_image] =>[orig_patent_app_number] => 09775231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/775231
Trench isolation method Jan 31, 2001 Issued
Array ( [id] => 7076955 [patent_doc_number] => 20010040292 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'Semiconductor device having a contact plug formed by a dual epitaxial layer and method for fabricating the same' [patent_app_type] => new [patent_app_number] => 09/770331 [patent_app_country] => US [patent_app_date] => 2001-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2481 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20010040292.pdf [firstpage_image] =>[orig_patent_app_number] => 09770331 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770331
Semiconductor device having a contact plug formed by a dual epitaxial layer and method for fabricating the same Jan 25, 2001 Abandoned
Array ( [id] => 6886594 [patent_doc_number] => 20010019863 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-09-06 [patent_title] => 'Method of forming a polycrystalline silicon layer' [patent_app_type] => new [patent_app_number] => 09/748871 [patent_app_country] => US [patent_app_date] => 2000-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2995 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0019/20010019863.pdf [firstpage_image] =>[orig_patent_app_number] => 09748871 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/748871
Method of forming a polycrystalline silicon layer Dec 27, 2000 Issued
Array ( [id] => 1517248 [patent_doc_number] => 06500718 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method for fabricating semiconductor device' [patent_app_type] => B2 [patent_app_number] => 09/747621 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3137 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500718.pdf [firstpage_image] =>[orig_patent_app_number] => 09747621 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/747621
Method for fabricating semiconductor device Dec 21, 2000 Issued
Array ( [id] => 7645715 [patent_doc_number] => 06472254 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-10-29 [patent_title] => 'Integrated photovoltaic switch with integrated power device including etching backside of substrate' [patent_app_type] => B2 [patent_app_number] => 09/746321 [patent_app_country] => US [patent_app_date] => 2000-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4746 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 18 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472254.pdf [firstpage_image] =>[orig_patent_app_number] => 09746321 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746321
Integrated photovoltaic switch with integrated power device including etching backside of substrate Dec 20, 2000 Issued
Array ( [id] => 7041033 [patent_doc_number] => 20010005622 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-06-28 [patent_title] => 'Method for manufacturing gate electrode with vertical side profile' [patent_app_type] => new-utility [patent_app_number] => 09/736132 [patent_app_country] => US [patent_app_date] => 2000-12-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1708 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20010005622.pdf [firstpage_image] =>[orig_patent_app_number] => 09736132 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/736132
Method for manufacturing gate electrode with vertical side profile Dec 14, 2000 Abandoned
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