Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6725218 [patent_doc_number] => 20030207530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2003-11-06 [patent_title] => 'Shallow trench isolation process for reduced junction leakage' [patent_app_type] => new [patent_app_number] => 09/729154 [patent_app_country] => US [patent_app_date] => 2000-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2995 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20030207530.pdf [firstpage_image] =>[orig_patent_app_number] => 09729154 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/729154
Shallow trench isolation process for reduced junction leakage Dec 3, 2000 Abandoned
Array ( [id] => 6875128 [patent_doc_number] => 20010000247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-04-12 [patent_title] => 'Semiconductor device manufacturing method' [patent_app_type] => new-utility [patent_app_number] => 09/726384 [patent_app_country] => US [patent_app_date] => 2000-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4761 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000247.pdf [firstpage_image] =>[orig_patent_app_number] => 09726384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726384
Semiconductor device manufacturing method including forming FOX with dual oxidation Nov 30, 2000 Issued
Array ( [id] => 1459400 [patent_doc_number] => 06391727 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Method of manufacturing a semiconductor device utilizing a(Al2O3)X-(TiO2)1-X gate dielectric film' [patent_app_type] => B1 [patent_app_number] => 09/722351 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 2149 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/391/06391727.pdf [firstpage_image] =>[orig_patent_app_number] => 09722351 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722351
Method of manufacturing a semiconductor device utilizing a(Al2O3)X-(TiO2)1-X gate dielectric film Nov 27, 2000 Issued
Array ( [id] => 1336571 [patent_doc_number] => 06593240 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Two step chemical mechanical polishing process' [patent_app_type] => B1 [patent_app_number] => 09/723802 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3896 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/593/06593240.pdf [firstpage_image] =>[orig_patent_app_number] => 09723802 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/723802
Two step chemical mechanical polishing process Nov 27, 2000 Issued
Array ( [id] => 1517251 [patent_doc_number] => 06500719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-31 [patent_title] => 'Method of manufacturing a MOSFET of an elevated source/drain structure with SEG in facet' [patent_app_type] => B1 [patent_app_number] => 09/722032 [patent_app_country] => US [patent_app_date] => 2000-11-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 3507 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/500/06500719.pdf [firstpage_image] =>[orig_patent_app_number] => 09722032 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/722032
Method of manufacturing a MOSFET of an elevated source/drain structure with SEG in facet Nov 26, 2000 Issued
Array ( [id] => 1532516 [patent_doc_number] => 06410403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-25 [patent_title] => 'Method for planarizing a shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/703831 [patent_app_country] => US [patent_app_date] => 2000-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2225 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/410/06410403.pdf [firstpage_image] =>[orig_patent_app_number] => 09703831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/703831
Method for planarizing a shallow trench isolation Nov 1, 2000 Issued
Array ( [id] => 1415359 [patent_doc_number] => 06511888 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step' [patent_app_type] => B1 [patent_app_number] => 09/697302 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 6276 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511888.pdf [firstpage_image] =>[orig_patent_app_number] => 09697302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697302
Method of fabricating a semiconductor device using trench isolation method including hydrogen annealing step Oct 26, 2000 Issued
Array ( [id] => 1358662 [patent_doc_number] => 06573154 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-03 [patent_title] => 'High aspect ratio trench isolation process for surface micromachined sensors and actuators' [patent_app_type] => B1 [patent_app_number] => 09/696082 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 19 [patent_no_of_words] => 2662 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/573/06573154.pdf [firstpage_image] =>[orig_patent_app_number] => 09696082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696082
High aspect ratio trench isolation process for surface micromachined sensors and actuators Oct 25, 2000 Issued
Array ( [id] => 1386024 [patent_doc_number] => 06548372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Forming sidewall oxide layers for trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/685531 [patent_app_country] => US [patent_app_date] => 2000-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2158 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548372.pdf [firstpage_image] =>[orig_patent_app_number] => 09685531 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/685531
Forming sidewall oxide layers for trench isolation Oct 9, 2000 Issued
Array ( [id] => 1520696 [patent_doc_number] => 06413835 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Semiconductor structure and fabrication method of shallow and deep trenches' [patent_app_type] => B1 [patent_app_number] => 09/662842 [patent_app_country] => US [patent_app_date] => 2000-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 3313 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 29 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/413/06413835.pdf [firstpage_image] =>[orig_patent_app_number] => 09662842 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662842
Semiconductor structure and fabrication method of shallow and deep trenches Sep 14, 2000 Issued
Array ( [id] => 1449844 [patent_doc_number] => 06455335 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step' [patent_app_type] => B1 [patent_app_number] => 09/653624 [patent_app_country] => US [patent_app_date] => 2000-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 9056 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/455/06455335.pdf [firstpage_image] =>[orig_patent_app_number] => 09653624 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/653624
Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step Aug 30, 2000 Issued
Array ( [id] => 1453523 [patent_doc_number] => 06461923 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Sidewall spacer etch process for improved silicide formation' [patent_app_type] => B1 [patent_app_number] => 09/639816 [patent_app_country] => US [patent_app_date] => 2000-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 10 [patent_no_of_words] => 6091 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461923.pdf [firstpage_image] =>[orig_patent_app_number] => 09639816 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639816
Sidewall spacer etch process for improved silicide formation Aug 16, 2000 Issued
Array ( [id] => 1409150 [patent_doc_number] => 06528361 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Process for preparing a polycrystalline silicon thin film' [patent_app_type] => B1 [patent_app_number] => 09/639212 [patent_app_country] => US [patent_app_date] => 2000-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 1944 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528361.pdf [firstpage_image] =>[orig_patent_app_number] => 09639212 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/639212
Process for preparing a polycrystalline silicon thin film Aug 13, 2000 Issued
Array ( [id] => 1494896 [patent_doc_number] => 06403431 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-11 [patent_title] => 'Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits' [patent_app_type] => B1 [patent_app_number] => 09/632582 [patent_app_country] => US [patent_app_date] => 2000-08-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 15 [patent_no_of_words] => 4892 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/403/06403431.pdf [firstpage_image] =>[orig_patent_app_number] => 09632582 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/632582
Method of forming in an insulating layer a trench that exceeds the photolithographic resolution limits Aug 6, 2000 Issued
09/629172 METHOD TO HARDEN SHALLOW TRENCH ISOLATION AGAINST TOTAL IONIZING DOSE RADIATION Jul 30, 2000 Abandoned
Array ( [id] => 1416032 [patent_doc_number] => 06518147 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-11 [patent_title] => 'Process for manufacturing an SOI wafer by oxidation of buried channels' [patent_app_type] => B1 [patent_app_number] => 09/625112 [patent_app_country] => US [patent_app_date] => 2000-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 23 [patent_no_of_words] => 3054 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/518/06518147.pdf [firstpage_image] =>[orig_patent_app_number] => 09625112 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/625112
Process for manufacturing an SOI wafer by oxidation of buried channels Jul 24, 2000 Issued
Array ( [id] => 1375935 [patent_doc_number] => 06559026 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Trench fill with HDP-CVD process including coupled high power density plasma deposition' [patent_app_type] => B1 [patent_app_number] => 09/579822 [patent_app_country] => US [patent_app_date] => 2000-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 11871 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/559/06559026.pdf [firstpage_image] =>[orig_patent_app_number] => 09579822 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/579822
Trench fill with HDP-CVD process including coupled high power density plasma deposition May 24, 2000 Issued
Array ( [id] => 1209312 [patent_doc_number] => 06713359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Semiconductor device and method of manufacturing the same including raised source/drain comprising SiGe or SiC' [patent_app_type] => B1 [patent_app_number] => 09/564191 [patent_app_country] => US [patent_app_date] => 2000-05-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 7521 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/713/06713359.pdf [firstpage_image] =>[orig_patent_app_number] => 09564191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/564191
Semiconductor device and method of manufacturing the same including raised source/drain comprising SiGe or SiC May 3, 2000 Issued
09/563752 Novel polysilicon material and semiconductor devices formed therefrom Apr 30, 2000 Abandoned
Array ( [id] => 1419195 [patent_doc_number] => 06506657 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Process for forming damascene-type isolation structure for BJT device formed in trench' [patent_app_type] => B1 [patent_app_number] => 09/552412 [patent_app_country] => US [patent_app_date] => 2000-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 2451 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506657.pdf [firstpage_image] =>[orig_patent_app_number] => 09552412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/552412
Process for forming damascene-type isolation structure for BJT device formed in trench Apr 18, 2000 Issued
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