Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1514517 [patent_doc_number] => 06420247 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-16 [patent_title] => 'Method of forming structures on a semiconductor including doping profiles using thickness of photoresist' [patent_app_type] => B1 [patent_app_number] => 09/546402 [patent_app_country] => US [patent_app_date] => 2000-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2219 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/420/06420247.pdf [firstpage_image] =>[orig_patent_app_number] => 09546402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/546402
Method of forming structures on a semiconductor including doping profiles using thickness of photoresist Apr 9, 2000 Issued
Array ( [id] => 1419250 [patent_doc_number] => 06506661 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-14 [patent_title] => 'Isolation method to replace STI for deep sub-micron VLSI process including epitaxial silicon' [patent_app_type] => B1 [patent_app_number] => 09/541482 [patent_app_country] => US [patent_app_date] => 2000-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 3208 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/506/06506661.pdf [firstpage_image] =>[orig_patent_app_number] => 09541482 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541482
Isolation method to replace STI for deep sub-micron VLSI process including epitaxial silicon Apr 2, 2000 Issued
Array ( [id] => 1390703 [patent_doc_number] => 06544887 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-08 [patent_title] => 'Polycide etch process' [patent_app_type] => B1 [patent_app_number] => 09/541432 [patent_app_country] => US [patent_app_date] => 2000-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3109 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/544/06544887.pdf [firstpage_image] =>[orig_patent_app_number] => 09541432 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/541432
Polycide etch process Mar 30, 2000 Issued
Array ( [id] => 4304104 [patent_doc_number] => 06326290 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET' [patent_app_type] => 1 [patent_app_number] => 9/531782 [patent_app_country] => US [patent_app_date] => 2000-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 14 [patent_no_of_words] => 2338 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 248 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/326/06326290.pdf [firstpage_image] =>[orig_patent_app_number] => 531782 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/531782
Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET Mar 20, 2000 Issued
Array ( [id] => 1523711 [patent_doc_number] => 06352908 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-05 [patent_title] => 'Method for reducing nitride residue in a LOCOS isolation area' [patent_app_type] => B1 [patent_app_number] => 09/519732 [patent_app_country] => US [patent_app_date] => 2000-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2828 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/352/06352908.pdf [firstpage_image] =>[orig_patent_app_number] => 09519732 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/519732
Method for reducing nitride residue in a LOCOS isolation area Mar 2, 2000 Issued
Array ( [id] => 7645678 [patent_doc_number] => 06472291 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Planarization process to achieve improved uniformity across semiconductor wafers' [patent_app_type] => B1 [patent_app_number] => 09/492541 [patent_app_country] => US [patent_app_date] => 2000-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3667 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472291.pdf [firstpage_image] =>[orig_patent_app_number] => 09492541 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/492541
Planarization process to achieve improved uniformity across semiconductor wafers Jan 26, 2000 Issued
Array ( [id] => 4324834 [patent_doc_number] => 06249035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect' [patent_app_type] => 1 [patent_app_number] => 9/480268 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 10 [patent_no_of_words] => 4143 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249035.pdf [firstpage_image] =>[orig_patent_app_number] => 480268 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/480268
LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect Jan 10, 2000 Issued
Array ( [id] => 4310421 [patent_doc_number] => 06316329 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Forming a trench mask comprising a DLC and ASH protecting layer' [patent_app_type] => 1 [patent_app_number] => 9/473121 [patent_app_country] => US [patent_app_date] => 1999-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 36 [patent_no_of_words] => 6326 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316329.pdf [firstpage_image] =>[orig_patent_app_number] => 473121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/473121
Forming a trench mask comprising a DLC and ASH protecting layer Dec 27, 1999 Issued
Array ( [id] => 1424286 [patent_doc_number] => 06503806 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-07 [patent_title] => 'Method for forming gate electrode of a semiconductor device with dual spacer to protect metal portion of gate' [patent_app_type] => B1 [patent_app_number] => 09/472202 [patent_app_country] => US [patent_app_date] => 1999-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1585 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/503/06503806.pdf [firstpage_image] =>[orig_patent_app_number] => 09472202 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/472202
Method for forming gate electrode of a semiconductor device with dual spacer to protect metal portion of gate Dec 26, 1999 Issued
Array ( [id] => 1433339 [patent_doc_number] => 06340629 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-22 [patent_title] => 'Method for forming gate electrodes of semiconductor device using a separated WN layer' [patent_app_type] => B1 [patent_app_number] => 09/466752 [patent_app_country] => US [patent_app_date] => 1999-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1350 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/340/06340629.pdf [firstpage_image] =>[orig_patent_app_number] => 09466752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/466752
Method for forming gate electrodes of semiconductor device using a separated WN layer Dec 16, 1999 Issued
Array ( [id] => 1446599 [patent_doc_number] => 06368937 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-09 [patent_title] => 'Method of manufacturing semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/456532 [patent_app_country] => US [patent_app_date] => 1999-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 23 [patent_no_of_words] => 4988 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/368/06368937.pdf [firstpage_image] =>[orig_patent_app_number] => 09456532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/456532
Method of manufacturing semiconductor device Dec 7, 1999 Issued
Array ( [id] => 1453512 [patent_doc_number] => 06461919 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method for fabricating semiconductor device with different gate oxide compositions' [patent_app_type] => B1 [patent_app_number] => 09/450512 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 26 [patent_no_of_words] => 8514 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461919.pdf [firstpage_image] =>[orig_patent_app_number] => 09450512 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/450512
Method for fabricating semiconductor device with different gate oxide compositions Nov 29, 1999 Issued
Array ( [id] => 1485234 [patent_doc_number] => 06365467 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-02 [patent_title] => 'Method of forming gate oxide layer in semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/436780 [patent_app_country] => US [patent_app_date] => 1999-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1325 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/365/06365467.pdf [firstpage_image] =>[orig_patent_app_number] => 09436780 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/436780
Method of forming gate oxide layer in semiconductor device Nov 7, 1999 Issued
Array ( [id] => 4324820 [patent_doc_number] => 06329253 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-11 [patent_title] => 'Thick oxide MOS device used in ESD protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/434922 [patent_app_country] => US [patent_app_date] => 1999-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 1908 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/329/06329253.pdf [firstpage_image] =>[orig_patent_app_number] => 434922 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/434922
Thick oxide MOS device used in ESD protection circuit Nov 4, 1999 Issued
Array ( [id] => 1245689 [patent_doc_number] => 06677207 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Vanishingly small integrated circuit diode' [patent_app_type] => B1 [patent_app_number] => 09/435322 [patent_app_country] => US [patent_app_date] => 1999-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 2022 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/677/06677207.pdf [firstpage_image] =>[orig_patent_app_number] => 09435322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435322
Vanishingly small integrated circuit diode Nov 3, 1999 Issued
Array ( [id] => 4289835 [patent_doc_number] => 06235599 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Fabrication of a shallow doped junction having low sheet resistance using multiple implantations' [patent_app_type] => 1 [patent_app_number] => 9/426402 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4126 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235599.pdf [firstpage_image] =>[orig_patent_app_number] => 426402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/426402
Fabrication of a shallow doped junction having low sheet resistance using multiple implantations Oct 24, 1999 Issued
Array ( [id] => 4095281 [patent_doc_number] => 06096647 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Method to form CoSi.sub.2 on shallow junction by Si implantation' [patent_app_type] => 1 [patent_app_number] => 9/425311 [patent_app_country] => US [patent_app_date] => 1999-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 1487 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096647.pdf [firstpage_image] =>[orig_patent_app_number] => 425311 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/425311
Method to form CoSi.sub.2 on shallow junction by Si implantation Oct 24, 1999 Issued
Array ( [id] => 7645668 [patent_doc_number] => 06472301 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-29 [patent_title] => 'Method and structure for shallow trench isolation' [patent_app_type] => B1 [patent_app_number] => 09/421161 [patent_app_country] => US [patent_app_date] => 1999-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1970 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 11 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/472/06472301.pdf [firstpage_image] =>[orig_patent_app_number] => 09421161 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421161
Method and structure for shallow trench isolation Oct 18, 1999 Issued
Array ( [id] => 1347351 [patent_doc_number] => 06579784 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-17 [patent_title] => 'Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers' [patent_app_type] => B1 [patent_app_number] => 09/419511 [patent_app_country] => US [patent_app_date] => 1999-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2539 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/579/06579784.pdf [firstpage_image] =>[orig_patent_app_number] => 09419511 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/419511
Method for forming a metal gate integrated with a source and drain salicide process with oxynitride spacers Oct 17, 1999 Issued
Array ( [id] => 1102665 [patent_doc_number] => 06815762 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-11-09 [patent_title] => 'Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines' [patent_app_type] => B2 [patent_app_number] => 09/416959 [patent_app_country] => US [patent_app_date] => 1999-10-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 49 [patent_figures_cnt] => 58 [patent_no_of_words] => 10882 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 432 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/815/06815762.pdf [firstpage_image] =>[orig_patent_app_number] => 09416959 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/416959
Semiconductor integrated circuit device and process for manufacturing the same including spacers on bit lines Oct 12, 1999 Issued
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