
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1514517
[patent_doc_number] => 06420247
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[patent_issue_date] => 2002-07-16
[patent_title] => 'Method of forming structures on a semiconductor including doping profiles using thickness of photoresist'
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[patent_app_number] => 09/546402
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Array
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[patent_title] => 'Isolation method to replace STI for deep sub-micron VLSI process including epitaxial silicon'
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Array
(
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[patent_title] => 'Polycide etch process'
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[patent_app_number] => 09/541432
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Array
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[patent_issue_date] => 2001-12-04
[patent_title] => 'Low resistance self aligned extended gate structure utilizing A T or Y shaped gate structure for high performance deep submicron FET'
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[patent_app_number] => 9/531782
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Array
(
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[patent_title] => 'Method for reducing nitride residue in a LOCOS isolation area'
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Array
(
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Array
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[patent_title] => 'LOCOS mask for suppression of narrow space field oxide thinning and oxide punch through effect'
[patent_app_type] => 1
[patent_app_number] => 9/480268
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Array
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[patent_title] => 'Forming a trench mask comprising a DLC and ASH protecting layer'
[patent_app_type] => 1
[patent_app_number] => 9/473121
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Array
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[patent_title] => 'Method for forming gate electrode of a semiconductor device with dual spacer to protect metal portion of gate'
[patent_app_type] => B1
[patent_app_number] => 09/472202
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Array
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[patent_title] => 'Method for forming gate electrodes of semiconductor device using a separated WN layer'
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Array
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Array
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Array
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Array
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Array
(
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[patent_issue_date] => 2001-05-22
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Array
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