Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4318722 [patent_doc_number] => 06248637 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Process for manufacturing MOS Transistors having elevated source and drain regions' [patent_app_type] => 1 [patent_app_number] => 9/405831 [patent_app_country] => US [patent_app_date] => 1999-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 8 [patent_no_of_words] => 3740 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/248/06248637.pdf [firstpage_image] =>[orig_patent_app_number] => 405831 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/405831
Process for manufacturing MOS Transistors having elevated source and drain regions Sep 23, 1999 Issued
Array ( [id] => 1179953 [patent_doc_number] => 06740566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-05-25 [patent_title] => 'Ultra-thin resist shallow trench process using high selectivity nitride etch' [patent_app_type] => B2 [patent_app_number] => 09/398641 [patent_app_country] => US [patent_app_date] => 1999-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 4470 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/740/06740566.pdf [firstpage_image] =>[orig_patent_app_number] => 09398641 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/398641
Ultra-thin resist shallow trench process using high selectivity nitride etch Sep 16, 1999 Issued
Array ( [id] => 1012634 [patent_doc_number] => 06897105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-24 [patent_title] => 'Method of forming metal oxide gate structures and capacitor electrodes' [patent_app_type] => utility [patent_app_number] => 09/396642 [patent_app_country] => US [patent_app_date] => 1999-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 7 [patent_no_of_words] => 2934 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/897/06897105.pdf [firstpage_image] =>[orig_patent_app_number] => 09396642 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/396642
Method of forming metal oxide gate structures and capacitor electrodes Sep 14, 1999 Issued
Array ( [id] => 1398978 [patent_doc_number] => 06537884 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-25 [patent_title] => 'Semiconductor device and method of manufacturing the same including an offset-gate structure' [patent_app_type] => B1 [patent_app_number] => 09/389381 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 59 [patent_no_of_words] => 8027 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/537/06537884.pdf [firstpage_image] =>[orig_patent_app_number] => 09389381 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389381
Semiconductor device and method of manufacturing the same including an offset-gate structure Sep 2, 1999 Issued
Array ( [id] => 4250173 [patent_doc_number] => 06207534 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-27 [patent_title] => 'Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing' [patent_app_type] => 1 [patent_app_number] => 9/389632 [patent_app_country] => US [patent_app_date] => 1999-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2290 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/207/06207534.pdf [firstpage_image] =>[orig_patent_app_number] => 389632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/389632
Method to form narrow and wide shallow trench isolations with different trench depths to eliminate isolation oxide dishing Sep 2, 1999 Issued
Array ( [id] => 4269674 [patent_doc_number] => 06245615 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-12 [patent_title] => 'Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction' [patent_app_type] => 1 [patent_app_number] => 9/386181 [patent_app_country] => US [patent_app_date] => 1999-08-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 21 [patent_no_of_words] => 8531 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/245/06245615.pdf [firstpage_image] =>[orig_patent_app_number] => 386181 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/386181
Method and apparatus on (110) surfaces of silicon structures with conduction in the <110> direction Aug 30, 1999 Issued
09/379092 FORMING SIDEWALL OXIDE LAYERS FOR TRENCH ISOLATION Aug 22, 1999 Abandoned
Array ( [id] => 7026631 [patent_doc_number] => 20010013623 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'SIMPLIFIED METHOD OF PATTERNING POLYSILICON GATE IN A SEMICONDUCTOR DEVICE' [patent_app_type] => new [patent_app_number] => 09/365411 [patent_app_country] => US [patent_app_date] => 1999-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2628 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0013/20010013623.pdf [firstpage_image] =>[orig_patent_app_number] => 09365411 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/365411
Simplified method of patterning polysilicon gate in a semiconductor device including an oxime layer as a mask Aug 1, 1999 Issued
Array ( [id] => 1478121 [patent_doc_number] => 06451671 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-17 [patent_title] => 'Semiconductor device production method and apparatus' [patent_app_type] => B1 [patent_app_number] => 09/348472 [patent_app_country] => US [patent_app_date] => 1999-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 5003 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/451/06451671.pdf [firstpage_image] =>[orig_patent_app_number] => 09348472 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/348472
Semiconductor device production method and apparatus Jul 6, 1999 Issued
Array ( [id] => 1396505 [patent_doc_number] => 06531355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-03-11 [patent_title] => 'LDMOS device with self-aligned RESURF region and method of fabrication' [patent_app_type] => B2 [patent_app_number] => 09/346761 [patent_app_country] => US [patent_app_date] => 1999-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 3452 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/531/06531355.pdf [firstpage_image] =>[orig_patent_app_number] => 09346761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/346761
LDMOS device with self-aligned RESURF region and method of fabrication Jun 30, 1999 Issued
Array ( [id] => 4357709 [patent_doc_number] => 06191008 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer' [patent_app_type] => 1 [patent_app_number] => 9/344281 [patent_app_country] => US [patent_app_date] => 1999-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 2472 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/191/06191008.pdf [firstpage_image] =>[orig_patent_app_number] => 344281 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/344281
Method of forming SOI substrate which includes forming trenches during etching of top semiconductor layer Jun 29, 1999 Issued
Array ( [id] => 4235548 [patent_doc_number] => 06165870 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure' [patent_app_type] => 1 [patent_app_number] => 9/342501 [patent_app_country] => US [patent_app_date] => 1999-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 1645 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165870.pdf [firstpage_image] =>[orig_patent_app_number] => 342501 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/342501
Element isolation method for semiconductor devices including etching implanted region under said spacer to form a stepped trench structure Jun 28, 1999 Issued
Array ( [id] => 1441035 [patent_doc_number] => 06335258 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-01 [patent_title] => 'Method for making a thin film on a support and resulting structure including an additional thinning stage before heat treatment causes micro-cavities to separate substrate element' [patent_app_type] => B1 [patent_app_number] => 09/284801 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 3239 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/335/06335258.pdf [firstpage_image] =>[orig_patent_app_number] => 09284801 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/284801
Method for making a thin film on a support and resulting structure including an additional thinning stage before heat treatment causes micro-cavities to separate substrate element Jun 17, 1999 Issued
Array ( [id] => 6618310 [patent_doc_number] => 20020064919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-05-30 [patent_title] => 'METHOD OF FABRICATING GATE' [patent_app_type] => new [patent_app_number] => 09/335632 [patent_app_country] => US [patent_app_date] => 1999-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1599 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0064/20020064919.pdf [firstpage_image] =>[orig_patent_app_number] => 09335632 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/335632
METHOD OF FABRICATING GATE Jun 17, 1999 Abandoned
Array ( [id] => 4358279 [patent_doc_number] => 06255174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-03 [patent_title] => 'Mos transistor with dual pocket implant' [patent_app_type] => 1 [patent_app_number] => 9/334121 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2107 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 283 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/255/06255174.pdf [firstpage_image] =>[orig_patent_app_number] => 334121 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/334121
Mos transistor with dual pocket implant Jun 14, 1999 Issued
Array ( [id] => 4310264 [patent_doc_number] => 06316318 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-13 [patent_title] => 'Angled implant to build MOS transistors in contact holes' [patent_app_type] => 1 [patent_app_number] => 9/333771 [patent_app_country] => US [patent_app_date] => 1999-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 26 [patent_no_of_words] => 3216 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/316/06316318.pdf [firstpage_image] =>[orig_patent_app_number] => 333771 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/333771
Angled implant to build MOS transistors in contact holes Jun 14, 1999 Issued
Array ( [id] => 1119790 [patent_doc_number] => 06797601 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-28 [patent_title] => 'Methods for forming wordlines, transistor gates, and conductive interconnects' [patent_app_type] => B2 [patent_app_number] => 09/332271 [patent_app_country] => US [patent_app_date] => 1999-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2332 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/797/06797601.pdf [firstpage_image] =>[orig_patent_app_number] => 09332271 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/332271
Methods for forming wordlines, transistor gates, and conductive interconnects Jun 10, 1999 Issued
Array ( [id] => 7629861 [patent_doc_number] => 06818495 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-16 [patent_title] => 'Method for forming high purity silicon oxide field oxide isolation region' [patent_app_type] => B1 [patent_app_number] => 09/325951 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 4015 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 15 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/818/06818495.pdf [firstpage_image] =>[orig_patent_app_number] => 09325951 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325951
Method for forming high purity silicon oxide field oxide isolation region Jun 3, 1999 Issued
Array ( [id] => 1385841 [patent_doc_number] => 06548362 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-15 [patent_title] => 'Method of forming MOSFET with buried contact and air-gap gate structure' [patent_app_type] => B1 [patent_app_number] => 09/325811 [patent_app_country] => US [patent_app_date] => 1999-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 2369 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 332 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/548/06548362.pdf [firstpage_image] =>[orig_patent_app_number] => 09325811 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/325811
Method of forming MOSFET with buried contact and air-gap gate structure Jun 3, 1999 Issued
Array ( [id] => 4087050 [patent_doc_number] => 06133104 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall' [patent_app_type] => 1 [patent_app_number] => 9/323772 [patent_app_country] => US [patent_app_date] => 1999-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 3678 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133104.pdf [firstpage_image] =>[orig_patent_app_number] => 323772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/323772
Method of eliminating buried contact trench in MOSFET devices with self-aligned silicide including a silicon connection to the buried contact region which comprises a doped silicon sidewall May 31, 1999 Issued
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