Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4266943 [patent_doc_number] => 06306722 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-23 [patent_title] => 'Method for fabricating shallow trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/304143 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1631 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/306/06306722.pdf [firstpage_image] =>[orig_patent_app_number] => 304143 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304143
Method for fabricating shallow trench isolation structure May 2, 1999 Issued
Array ( [id] => 4356819 [patent_doc_number] => 06174759 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-16 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => 1 [patent_app_number] => 9/304412 [patent_app_country] => US [patent_app_date] => 1999-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 4664 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/174/06174759.pdf [firstpage_image] =>[orig_patent_app_number] => 304412 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/304412
Method of manufacturing a semiconductor device May 2, 1999 Issued
Array ( [id] => 6242475 [patent_doc_number] => 20020045318 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-04-18 [patent_title] => 'METHOD FOR MANUFACTURING MOS TRANSISTOR' [patent_app_type] => new [patent_app_number] => 09/303322 [patent_app_country] => US [patent_app_date] => 1999-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1322 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20020045318.pdf [firstpage_image] =>[orig_patent_app_number] => 09303322 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/303322
METHOD FOR MANUFACTURING MOS TRANSISTOR Apr 29, 1999 Abandoned
Array ( [id] => 4293892 [patent_doc_number] => 06197660 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Integration of CMP and wet or dry etching for STI' [patent_app_type] => 1 [patent_app_number] => 9/301223 [patent_app_country] => US [patent_app_date] => 1999-04-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 1561 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197660.pdf [firstpage_image] =>[orig_patent_app_number] => 301223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/301223
Integration of CMP and wet or dry etching for STI Apr 28, 1999 Issued
Array ( [id] => 4087064 [patent_doc_number] => 06133105 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-17 [patent_title] => 'Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure' [patent_app_type] => 1 [patent_app_number] => 9/300553 [patent_app_country] => US [patent_app_date] => 1999-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2600 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/133/06133105.pdf [firstpage_image] =>[orig_patent_app_number] => 300553 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/300553
Method of manufacturing borderless contact hole including a silicide layer on source/drain and sidewall of trench isolation structure Apr 26, 1999 Issued
Array ( [id] => 4419351 [patent_doc_number] => 06177304 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Self-aligned contact process using a poly-cap mask' [patent_app_type] => 1 [patent_app_number] => 9/298933 [patent_app_country] => US [patent_app_date] => 1999-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 2708 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177304.pdf [firstpage_image] =>[orig_patent_app_number] => 298933 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/298933
Self-aligned contact process using a poly-cap mask Apr 25, 1999 Issued
Array ( [id] => 4289957 [patent_doc_number] => 06235608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'STI process by method of in-situ multilayer dielectric deposition' [patent_app_type] => 1 [patent_app_number] => 9/292772 [patent_app_country] => US [patent_app_date] => 1999-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3944 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/235/06235608.pdf [firstpage_image] =>[orig_patent_app_number] => 292772 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/292772
STI process by method of in-situ multilayer dielectric deposition Apr 13, 1999 Issued
Array ( [id] => 4161600 [patent_doc_number] => 06107688 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Aluminum-containing films derived from using hydrogen and oxygen gas in sputter deposition' [patent_app_type] => 1 [patent_app_number] => 9/290532 [patent_app_country] => US [patent_app_date] => 1999-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 3984 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107688.pdf [firstpage_image] =>[orig_patent_app_number] => 290532 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/290532
Aluminum-containing films derived from using hydrogen and oxygen gas in sputter deposition Apr 11, 1999 Issued
Array ( [id] => 4293918 [patent_doc_number] => 06197662 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor processing method of forming field isolation oxide using a polybuffered mask which includes a base nitride layer on the substrate, and other semiconductor processing methods' [patent_app_type] => 1 [patent_app_number] => 9/288881 [patent_app_country] => US [patent_app_date] => 1999-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2282 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197662.pdf [firstpage_image] =>[orig_patent_app_number] => 288881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/288881
Semiconductor processing method of forming field isolation oxide using a polybuffered mask which includes a base nitride layer on the substrate, and other semiconductor processing methods Apr 8, 1999 Issued
Array ( [id] => 4182274 [patent_doc_number] => 06150223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-21 [patent_title] => 'Method for forming gate spacers with different widths' [patent_app_type] => 1 [patent_app_number] => 9/287881 [patent_app_country] => US [patent_app_date] => 1999-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 1307 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/150/06150223.pdf [firstpage_image] =>[orig_patent_app_number] => 287881 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/287881
Method for forming gate spacers with different widths Apr 6, 1999 Issued
Array ( [id] => 4405629 [patent_doc_number] => 06232202 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Method for manufacturing shallow trench isolation structure including a dual trench' [patent_app_type] => 1 [patent_app_number] => 9/286231 [patent_app_country] => US [patent_app_date] => 1999-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 2291 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232202.pdf [firstpage_image] =>[orig_patent_app_number] => 286231 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/286231
Method for manufacturing shallow trench isolation structure including a dual trench Apr 4, 1999 Issued
Array ( [id] => 4235713 [patent_doc_number] => 06165882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-26 [patent_title] => 'Polysilicon gate having a metal plug, for reduced gate resistance, within a trench extending into the polysilicon layer of the gate' [patent_app_type] => 1 [patent_app_number] => 9/283753 [patent_app_country] => US [patent_app_date] => 1999-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 2798 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/165/06165882.pdf [firstpage_image] =>[orig_patent_app_number] => 283753 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/283753
Polysilicon gate having a metal plug, for reduced gate resistance, within a trench extending into the polysilicon layer of the gate Apr 1, 1999 Issued
Array ( [id] => 4259525 [patent_doc_number] => 06204204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method and apparatus for depositing tantalum-based thin films with organmetallic precursor' [patent_app_type] => 1 [patent_app_number] => 9/282952 [patent_app_country] => US [patent_app_date] => 1999-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5977 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/204/06204204.pdf [firstpage_image] =>[orig_patent_app_number] => 282952 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282952
Method and apparatus for depositing tantalum-based thin films with organmetallic precursor Mar 31, 1999 Issued
Array ( [id] => 4153949 [patent_doc_number] => 06103559 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication' [patent_app_type] => 1 [patent_app_number] => 9/282033 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 24 [patent_no_of_words] => 7337 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103559.pdf [firstpage_image] =>[orig_patent_app_number] => 282033 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282033
Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication Mar 29, 1999 Issued
Array ( [id] => 4405467 [patent_doc_number] => 06232187 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-15 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => 1 [patent_app_number] => 9/280992 [patent_app_country] => US [patent_app_date] => 1999-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 79 [patent_no_of_words] => 11564 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/232/06232187.pdf [firstpage_image] =>[orig_patent_app_number] => 280992 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280992
Semiconductor device and manufacturing method thereof Mar 29, 1999 Issued
Array ( [id] => 4154899 [patent_doc_number] => 06103622 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device' [patent_app_type] => 1 [patent_app_number] => 9/282063 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4007 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103622.pdf [firstpage_image] =>[orig_patent_app_number] => 282063 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282063
Silicide process for mixed mode product with dual layer capacitor and polysilicon resistor which is protected with a capacitor protective oxide during silicidation of FET device Mar 28, 1999 Issued
Array ( [id] => 4154885 [patent_doc_number] => 06103621 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device' [patent_app_type] => 1 [patent_app_number] => 9/282062 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 4006 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/103/06103621.pdf [firstpage_image] =>[orig_patent_app_number] => 282062 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/282062
Silicide process for mixed mode product with dual layer capacitor which is protected by a capacitor protective oxide during silicidation of FET device Mar 28, 1999 Issued
Array ( [id] => 4101642 [patent_doc_number] => 06100142 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-08 [patent_title] => 'Method of fabricating sub-quarter-micron salicide polysilicon' [patent_app_type] => 1 [patent_app_number] => 9/280761 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 2564 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/100/06100142.pdf [firstpage_image] =>[orig_patent_app_number] => 280761 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280761
Method of fabricating sub-quarter-micron salicide polysilicon Mar 28, 1999 Issued
Array ( [id] => 1453603 [patent_doc_number] => 06461951 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers' [patent_app_type] => B1 [patent_app_number] => 09/280662 [patent_app_country] => US [patent_app_date] => 1999-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 12 [patent_no_of_words] => 3563 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/461/06461951.pdf [firstpage_image] =>[orig_patent_app_number] => 09280662 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/280662
Method of forming a sidewall spacer to prevent gouging of device junctions during interlayer dielectric etching including silicide growth over gate spacers Mar 28, 1999 Issued
Array ( [id] => 4215315 [patent_doc_number] => 06087227 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method for fabricating an electrostatic discharge protection circuit' [patent_app_type] => 1 [patent_app_number] => 9/276083 [patent_app_country] => US [patent_app_date] => 1999-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 3887 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/087/06087227.pdf [firstpage_image] =>[orig_patent_app_number] => 276083 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/276083
Method for fabricating an electrostatic discharge protection circuit Mar 24, 1999 Issued
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