Scott R. Wilson

Array ( [id] => 4406040 [patent_doc_number] => 06171930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Device isolation structure and device isolation method for a semiconductor power integrated circuit' [patent_app_type] => 1 [patent_app_number] => 9/233463 [patent_app_country] => US [patent_app_date] => 1999-01-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 30 [patent_no_of_words] => 4130 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/171/06171930.pdf [firstpage_image] =>[orig_patent_app_number] => 233463 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302306 [patent_doc_number] => 06251760 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-26 [patent_title] => 'Semiconductor device and its wiring and a fabrication method thereof' [patent_app_type] => 1 [patent_app_number] => 9/233171 [patent_app_country] => US [patent_app_date] => 1999-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 35 [patent_no_of_words] => 5804 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/251/06251760.pdf [firstpage_image] =>[orig_patent_app_number] => 233171 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1561138 [patent_doc_number] => 06362063 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Formation of low thermal budget shallow abrupt junctions for semiconductor devices' [patent_app_type] => B1 [patent_app_number] => 09/226773 [patent_app_country] => US [patent_app_date] => 1999-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 13 [patent_no_of_words] => 4195 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/362/06362063.pdf [firstpage_image] =>[orig_patent_app_number] => 09226773 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312795 [patent_doc_number] => 06242333 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Method to enhance the formation of nucleation sites on silicon structures and an improved silicon structure' [patent_app_type] => 1 [patent_app_number] => 9/225881 [patent_app_country] => US [patent_app_date] => 1999-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 9 [patent_no_of_words] => 3195 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242333.pdf [firstpage_image] =>[orig_patent_app_number] => 225881 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4354651 [patent_doc_number] => 06200865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-13 [patent_title] => 'Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate' [patent_app_type] => 1 [patent_app_number] => 9/205443 [patent_app_country] => US [patent_app_date] => 1998-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 18 [patent_no_of_words] => 5769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/200/06200865.pdf [firstpage_image] =>[orig_patent_app_number] => 205443 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4419754 [patent_doc_number] => 06177344 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'BPSG reflow method to reduce thermal budget for next generation device including heating in a steam ambient' [patent_app_type] => 1 [patent_app_number] => 9/199911 [patent_app_country] => US [patent_app_date] => 1998-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4182 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/177/06177344.pdf [firstpage_image] =>[orig_patent_app_number] => 199911 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4302634 [patent_doc_number] => 06187640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-13 [patent_title] => 'Semiconductor device manufacturing method including various oxidation steps with different concentration of chlorine to form a field oxide' [patent_app_type] => 1 [patent_app_number] => 9/193252 [patent_app_country] => US [patent_app_date] => 1998-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 22 [patent_no_of_words] => 4638 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/187/06187640.pdf [firstpage_image] =>[orig_patent_app_number] => 193252 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420901 [patent_doc_number] => 06225240 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Rapid acceleration methods for global planarization of spin-on films' [patent_app_type] => 1 [patent_app_number] => 9/191101 [patent_app_country] => US [patent_app_date] => 1998-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 27 [patent_no_of_words] => 15554 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225240.pdf [firstpage_image] =>[orig_patent_app_number] => 191101 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4420161 [patent_doc_number] => 06225173 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-01 [patent_title] => 'Recessed channel structure for manufacturing shallow source/drain extensions' [patent_app_type] => 1 [patent_app_number] => 9/187172 [patent_app_country] => US [patent_app_date] => 1998-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 5 [patent_no_of_words] => 2400 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/225/06225173.pdf [firstpage_image] =>[orig_patent_app_number] => 187172 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6224665 [patent_doc_number] => 20020004284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-01-10 [patent_title] => 'METHOD FOR FORMING A SHALLOW TRENCH ISOLATION STRUCTURE INCLUDING A DUMMY PATTERN IN THE WIDER TRENCH' [patent_app_type] => new [patent_app_number] => 09/187062 [patent_app_country] => US [patent_app_date] => 1998-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 1855 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 23 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0004/20020004284.pdf [firstpage_image] =>[orig_patent_app_number] => 09187062 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4376841 [patent_doc_number] => 06303394 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-16 [patent_title] => 'Global cluster pre-classification methodology' [patent_app_type] => 1 [patent_app_number] => 9/186052 [patent_app_country] => US [patent_app_date] => 1998-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2575 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/303/06303394.pdf [firstpage_image] =>[orig_patent_app_number] => 186052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4139068 [patent_doc_number] => 06060348 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-09 [patent_title] => 'Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology' [patent_app_type] => 1 [patent_app_number] => 9/184341 [patent_app_country] => US [patent_app_date] => 1998-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 1559 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/060/06060348.pdf [firstpage_image] =>[orig_patent_app_number] => 184341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4094717 [patent_doc_number] => 06096609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'ESD protection circuit and method for fabricating same using a plurality of dummy gate electrodes as a salicide mask for a drain' [patent_app_type] => 1 [patent_app_number] => 9/181802 [patent_app_country] => US [patent_app_date] => 1998-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 21 [patent_no_of_words] => 4099 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/096/06096609.pdf [firstpage_image] =>[orig_patent_app_number] => 181802 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4188376 [patent_doc_number] => 06153482 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method for fabricating LOCOS isolation having a planar surface which includes having the polish stop layer at a lower level than the LOCOS formation' [patent_app_type] => 1 [patent_app_number] => 9/174091 [patent_app_country] => US [patent_app_date] => 1998-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1297 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/153/06153482.pdf [firstpage_image] =>[orig_patent_app_number] => 174091 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4293083 [patent_doc_number] => 06197603 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-06 [patent_title] => 'Semiconductor device and manufacturing method thereof including a probe test step and a burn-in test step' [patent_app_type] => 1 [patent_app_number] => 9/157153 [patent_app_country] => US [patent_app_date] => 1998-09-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 22 [patent_no_of_words] => 8972 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/197/06197603.pdf [firstpage_image] =>[orig_patent_app_number] => 157153 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4234048 [patent_doc_number] => 06074930 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-13 [patent_title] => 'Method for forming a trench isolation structure comprising an interface treatment for trench liner and a subsequent annealing process' [patent_app_type] => 1 [patent_app_number] => 9/154782 [patent_app_country] => US [patent_app_date] => 1998-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3084 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/074/06074930.pdf [firstpage_image] =>[orig_patent_app_number] => 154782 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238521 [patent_doc_number] => 06080658 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-27 [patent_title] => 'Device protection structure for preventing plasma charging damage and vertical cross talk' [patent_app_type] => 1 [patent_app_number] => 9/151061 [patent_app_country] => US [patent_app_date] => 1998-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2543 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/080/06080658.pdf [firstpage_image] =>[orig_patent_app_number] => 151061 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4408237 [patent_doc_number] => 06300193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-10-09 [patent_title] => 'Flash memory with nanocrystalline silicon film floating gate' [patent_app_type] => 1 [patent_app_number] => 9/145721 [patent_app_country] => US [patent_app_date] => 1998-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 3010 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/300/06300193.pdf [firstpage_image] =>[orig_patent_app_number] => 145721 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 6474110 [patent_doc_number] => 20020022319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-21 [patent_title] => 'SEMICONDUCTOR PROCESSING METHODS OF FORMING DYNAMIC RANDOM ACCESS MEMORY (DRAM) CIRCUITRY' [patent_app_type] => new [patent_app_number] => 09/139691 [patent_app_country] => US [patent_app_date] => 1998-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 2441 [patent_no_of_claims] => 49 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0022/20020022319.pdf [firstpage_image] =>[orig_patent_app_number] => 09139691 [rel_patent_id] =>[rel_patent_doc_number] =>)