Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1409195 [patent_doc_number] => 06528364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-03-04 [patent_title] => 'Methods to form electronic devices and methods to form a material over a semiconductive substrate' [patent_app_type] => B1 [patent_app_number] => 09/138773 [patent_app_country] => US [patent_app_date] => 1998-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4373 [patent_no_of_claims] => 89 [patent_no_of_ind_claims] => 14 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/528/06528364.pdf [firstpage_image] =>[orig_patent_app_number] => 09138773 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/138773
Methods to form electronic devices and methods to form a material over a semiconductive substrate Aug 23, 1998 Issued
Array ( [id] => 4246396 [patent_doc_number] => 06136689 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-10-24 [patent_title] => 'Method of forming a micro solder ball for use in C4 bonding process' [patent_app_type] => 1 [patent_app_number] => 9/134363 [patent_app_country] => US [patent_app_date] => 1998-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 3816 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/136/06136689.pdf [firstpage_image] =>[orig_patent_app_number] => 134363 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134363
Method of forming a micro solder ball for use in C4 bonding process Aug 13, 1998 Issued
Array ( [id] => 4347980 [patent_doc_number] => 06214685 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-10 [patent_title] => 'Phosphate coating for varistor and method' [patent_app_type] => 1 [patent_app_number] => 9/108961 [patent_app_country] => US [patent_app_date] => 1998-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 4 [patent_no_of_words] => 2071 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/214/06214685.pdf [firstpage_image] =>[orig_patent_app_number] => 108961 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/108961
Phosphate coating for varistor and method Jul 1, 1998 Issued
Array ( [id] => 1196661 [patent_doc_number] => 06727148 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-04-27 [patent_title] => 'ULSI MOS with high dielectric constant gate insulator' [patent_app_type] => B1 [patent_app_number] => 09/109992 [patent_app_country] => US [patent_app_date] => 1998-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 8 [patent_no_of_words] => 2731 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/727/06727148.pdf [firstpage_image] =>[orig_patent_app_number] => 09109992 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/109992
ULSI MOS with high dielectric constant gate insulator Jun 29, 1998 Issued
Array ( [id] => 4153109 [patent_doc_number] => 06107145 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for forming a field effect transistor' [patent_app_type] => 1 [patent_app_number] => 9/079901 [patent_app_country] => US [patent_app_date] => 1998-05-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2059 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/107/06107145.pdf [firstpage_image] =>[orig_patent_app_number] => 079901 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/079901
Method for forming a field effect transistor May 14, 1998 Issued
Array ( [id] => 1595543 [patent_doc_number] => 06492234 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-10 [patent_title] => 'Process for the selective formation of salicide on active areas of MOS devices' [patent_app_type] => B1 [patent_app_number] => 09/076613 [patent_app_country] => US [patent_app_date] => 1998-05-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 27 [patent_no_of_words] => 3180 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/492/06492234.pdf [firstpage_image] =>[orig_patent_app_number] => 09076613 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/076613
Process for the selective formation of salicide on active areas of MOS devices May 11, 1998 Issued
Array ( [id] => 1415431 [patent_doc_number] => 06511893 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-01-28 [patent_title] => 'Radiation hardened semiconductor device' [patent_app_type] => B1 [patent_app_number] => 09/072932 [patent_app_country] => US [patent_app_date] => 1998-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3144 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/511/06511893.pdf [firstpage_image] =>[orig_patent_app_number] => 09072932 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/072932
Radiation hardened semiconductor device May 4, 1998 Issued
Array ( [id] => 4359266 [patent_doc_number] => 06169026 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer' [patent_app_type] => 1 [patent_app_number] => 9/065982 [patent_app_country] => US [patent_app_date] => 1998-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2097 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/169/06169026.pdf [firstpage_image] =>[orig_patent_app_number] => 065982 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/065982
Method for planarization of semiconductor device including pumping out dopants from planarization layer separately from flowing said layer Apr 23, 1998 Issued
Array ( [id] => 4181137 [patent_doc_number] => 06020230 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-01 [patent_title] => 'Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion' [patent_app_type] => 1 [patent_app_number] => 9/064261 [patent_app_country] => US [patent_app_date] => 1998-04-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 9 [patent_no_of_words] => 3030 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 193 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/020/06020230.pdf [firstpage_image] =>[orig_patent_app_number] => 064261 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/064261
Process to fabricate planarized deep-shallow trench isolation having upper and lower portions with oxidized semiconductor trench fill in the upper portion and semiconductor trench fill in the lower portion Apr 21, 1998 Issued
Array ( [id] => 4222008 [patent_doc_number] => 06010928 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-01-04 [patent_title] => 'High density transistor component and its manufacturing method' [patent_app_type] => 1 [patent_app_number] => 9/063302 [patent_app_country] => US [patent_app_date] => 1998-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 19 [patent_no_of_words] => 2091 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/010/06010928.pdf [firstpage_image] =>[orig_patent_app_number] => 063302 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/063302
High density transistor component and its manufacturing method Apr 20, 1998 Issued
Array ( [id] => 7028162 [patent_doc_number] => 20010014506 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-08-16 [patent_title] => 'METHOD FOR FORMING AN ISOLATION REGION IN A SEMICONDUCTOR DEVICE AND RESULTING STRUCTURE USING A TWO STEP OXIDATION PROCESS' [patent_app_type] => new [patent_app_number] => 09/062291 [patent_app_country] => US [patent_app_date] => 1998-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 6097 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 31 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0014/20010014506.pdf [firstpage_image] =>[orig_patent_app_number] => 09062291 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/062291
Method for forming an isolation region in a semiconductor device and resulting structure using a two step oxidation process Apr 16, 1998 Issued
Array ( [id] => 3910758 [patent_doc_number] => 06001694 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-14 [patent_title] => 'Manufacturing method for integrated circuit dielectric layer' [patent_app_type] => 1 [patent_app_number] => 9/059752 [patent_app_country] => US [patent_app_date] => 1998-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2482 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/001/06001694.pdf [firstpage_image] =>[orig_patent_app_number] => 059752 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/059752
Manufacturing method for integrated circuit dielectric layer Apr 13, 1998 Issued
Array ( [id] => 4237248 [patent_doc_number] => 06090682 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Isolation film of semiconductor device and method for fabricating the same comprising a lower isolation film with a upper isolation film formed on top' [patent_app_type] => 1 [patent_app_number] => 9/057563 [patent_app_country] => US [patent_app_date] => 1998-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 2196 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/090/06090682.pdf [firstpage_image] =>[orig_patent_app_number] => 057563 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/057563
Isolation film of semiconductor device and method for fabricating the same comprising a lower isolation film with a upper isolation film formed on top Apr 8, 1998 Issued
Array ( [id] => 3944392 [patent_doc_number] => 05998278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Method of fabricating shallow trench isolation structures using a oxidized polysilicon trench mask' [patent_app_type] => 1 [patent_app_number] => 9/056230 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 12 [patent_no_of_words] => 1584 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/998/05998278.pdf [firstpage_image] =>[orig_patent_app_number] => 056230 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/056230
Method of fabricating shallow trench isolation structures using a oxidized polysilicon trench mask Apr 6, 1998 Issued
Array ( [id] => 1528190 [patent_doc_number] => 06479410 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-11-12 [patent_title] => 'Processing method for object to be processed including a pre-coating step to seal fluorine' [patent_app_type] => B2 [patent_app_number] => 09/055910 [patent_app_country] => US [patent_app_date] => 1998-04-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 14 [patent_no_of_words] => 4713 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/479/06479410.pdf [firstpage_image] =>[orig_patent_app_number] => 09055910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055910
Processing method for object to be processed including a pre-coating step to seal fluorine Apr 6, 1998 Issued
Array ( [id] => 4219074 [patent_doc_number] => 06040231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Method of fabricating a shallow trench isolation structure which includes using a salicide process to form an aslope periphery at the top corner of the substrate' [patent_app_type] => 1 [patent_app_number] => 9/055684 [patent_app_country] => US [patent_app_date] => 1998-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 11 [patent_no_of_words] => 1511 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/040/06040231.pdf [firstpage_image] =>[orig_patent_app_number] => 055684 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/055684
Method of fabricating a shallow trench isolation structure which includes using a salicide process to form an aslope periphery at the top corner of the substrate Apr 5, 1998 Issued
Array ( [id] => 4327761 [patent_doc_number] => 06319847 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-20 [patent_title] => 'Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique' [patent_app_type] => 1 [patent_app_number] => 9/050561 [patent_app_country] => US [patent_app_date] => 1998-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 1901 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 86 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/319/06319847.pdf [firstpage_image] =>[orig_patent_app_number] => 050561 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/050561
Semiconductor device using a thermal treatment of the device in a pressurized steam ambient as a planarization technique Mar 29, 1998 Issued
Array ( [id] => 6209218 [patent_doc_number] => 20020072157 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'SEMICONDUCTOR DEVICE HAVING A SEMICONDUCTOR THIN FILM CONTAINING LOW CONCENTRATION OF UNBOUND HYDROGEN ATOMS AND METHOD OF MANUFACTURING THE SAME' [patent_app_type] => new [patent_app_number] => 09/049353 [patent_app_country] => US [patent_app_date] => 1998-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7653 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 43 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0072/20020072157.pdf [firstpage_image] =>[orig_patent_app_number] => 09049353 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/049353
Semiconductor device having a semiconductor thin film containing low concentration of unbound hydrogen atoms and method of manufacturing the same Mar 26, 1998 Issued
Array ( [id] => 4312108 [patent_doc_number] => 06242287 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-05 [patent_title] => 'Semiconductor device manufacturing method, press die and guide rail including forming a crack perpendicular to an extension of the sealing resin' [patent_app_type] => 1 [patent_app_number] => 9/044928 [patent_app_country] => US [patent_app_date] => 1998-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 38 [patent_no_of_words] => 11508 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/242/06242287.pdf [firstpage_image] =>[orig_patent_app_number] => 044928 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/044928
Semiconductor device manufacturing method, press die and guide rail including forming a crack perpendicular to an extension of the sealing resin Mar 19, 1998 Issued
Array ( [id] => 4353051 [patent_doc_number] => 06218198 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Method and apparatus for evaluating semiconductor film, and method for producing the semiconductor film' [patent_app_type] => 1 [patent_app_number] => 9/032243 [patent_app_country] => US [patent_app_date] => 1998-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3746 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/218/06218198.pdf [firstpage_image] =>[orig_patent_app_number] => 032243 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/032243
Method and apparatus for evaluating semiconductor film, and method for producing the semiconductor film Feb 26, 1998 Issued
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