
Scott R. Wilson
Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )
| Most Active Art Unit | 2826 |
| Art Unit(s) | 2826 |
| Total Applications | 901 |
| Issued Applications | 779 |
| Pending Applications | 16 |
| Abandoned Applications | 106 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8193010
[patent_doc_number] => 20120119355
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2012-05-17
[patent_title] => 'INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 12/946445
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/946445 | Integrated circuit structure and method of forming the same | Nov 14, 2010 | Issued |
Array
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[patent_title] => 'METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME'
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Array
(
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[patent_title] => 'Source tip optimization for high voltage transistor devices'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/944959 | Source tip optimization for high voltage transistor devices | Nov 11, 2010 | Issued |
Array
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[id] => 8198547
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[patent_issue_date] => 2012-05-17
[patent_title] => 'METHOD OF FABRICATING A SILICIDE LAYER'
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[patent_app_number] => 12/944738
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Array
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Array
(
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[patent_title] => 'Chalcogenide Containing Semiconductors with Chalcogenide Gradient'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/944119 | Chalcogenide containing semiconductors with chalcogenide gradient | Nov 10, 2010 | Issued |
Array
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[patent_issue_date] => 2012-05-17
[patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS'
[patent_app_type] => utility
[patent_app_number] => 12/943973
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/943973 | Semiconductor structure having wide and narrow deep trenches with different materials | Nov 10, 2010 | Issued |
Array
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[id] => 6055203
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[patent_issue_date] => 2011-05-12
[patent_title] => 'ADHESIVE TAPE FOR RESIN-ENCAPSULATING AND METHOD OF MANUFACTURE OF RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE'
[patent_app_type] => utility
[patent_app_number] => 12/944459
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Array
(
[id] => 8538286
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[patent_title] => 'Process for fabricating a heterostructure with minimized stress'
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Array
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[id] => 8340034
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[patent_title] => 'Negative thermal expansion system (NTES) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging'
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Array
(
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[patent_title] => 'CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT'
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Array
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Array
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Array
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Array
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Array
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