Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8193010 [patent_doc_number] => 20120119355 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURE AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/946445 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 2079 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119355.pdf [firstpage_image] =>[orig_patent_app_number] => 12946445 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946445
Integrated circuit structure and method of forming the same Nov 14, 2010 Issued
Array ( [id] => 6189095 [patent_doc_number] => 20110171800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-14 [patent_title] => 'METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME' [patent_app_type] => utility [patent_app_number] => 12/944870 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3878 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0171/20110171800.pdf [firstpage_image] =>[orig_patent_app_number] => 12944870 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944870
METHOD OF FORMING SEMICONDUCTOR DEVICES WITH BURIED GATE ELECTRODES AND DEVICES FORMED BY THE SAME Nov 11, 2010 Abandoned
Array ( [id] => 9216226 [patent_doc_number] => 08629026 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-01-14 [patent_title] => 'Source tip optimization for high voltage transistor devices' [patent_app_type] => utility [patent_app_number] => 12/944959 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5967 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12944959 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944959
Source tip optimization for high voltage transistor devices Nov 11, 2010 Issued
Array ( [id] => 8198547 [patent_doc_number] => 20120122288 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'METHOD OF FABRICATING A SILICIDE LAYER' [patent_app_type] => utility [patent_app_number] => 12/944738 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2124 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20120122288.pdf [firstpage_image] =>[orig_patent_app_number] => 12944738 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944738
METHOD OF FABRICATING A SILICIDE LAYER Nov 11, 2010 Abandoned
Array ( [id] => 7750455 [patent_doc_number] => 20120025299 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES' [patent_app_type] => utility [patent_app_number] => 12/945249 [patent_app_country] => US [patent_app_date] => 2010-11-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3781 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0025/20120025299.pdf [firstpage_image] =>[orig_patent_app_number] => 12945249 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/945249
METHOD FOR FABRICATING SEMICONDUCTOR DEVICE WITH BURIED GATES Nov 11, 2010 Abandoned
Array ( [id] => 8192674 [patent_doc_number] => 20120119177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Chalcogenide Containing Semiconductors with Chalcogenide Gradient' [patent_app_type] => utility [patent_app_number] => 12/944119 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2153 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20120119177.pdf [firstpage_image] =>[orig_patent_app_number] => 12944119 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944119
Chalcogenide containing semiconductors with chalcogenide gradient Nov 10, 2010 Issued
Array ( [id] => 8198568 [patent_doc_number] => 20120122303 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'SEMICONDUCTOR STRUCTURE HAVING WIDE AND NARROW DEEP TRENCHES WITH DIFFERENT MATERIALS' [patent_app_type] => utility [patent_app_number] => 12/943973 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3044 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0122/20120122303.pdf [firstpage_image] =>[orig_patent_app_number] => 12943973 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943973
Semiconductor structure having wide and narrow deep trenches with different materials Nov 10, 2010 Issued
Array ( [id] => 6055203 [patent_doc_number] => 20110111563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'ADHESIVE TAPE FOR RESIN-ENCAPSULATING AND METHOD OF MANUFACTURE OF RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/944459 [patent_app_country] => US [patent_app_date] => 2010-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6948 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0111/20110111563.pdf [firstpage_image] =>[orig_patent_app_number] => 12944459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/944459
ADHESIVE TAPE FOR RESIN-ENCAPSULATING AND METHOD OF MANUFACTURE OF RESIN-ENCAPSULATED SEMICONDUCTOR DEVICE Nov 10, 2010 Abandoned
Array ( [id] => 8538286 [patent_doc_number] => 08314007 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-20 [patent_title] => 'Process for fabricating a heterostructure with minimized stress' [patent_app_type] => utility [patent_app_number] => 12/943693 [patent_app_country] => US [patent_app_date] => 2010-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 5198 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12943693 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/943693
Process for fabricating a heterostructure with minimized stress Nov 9, 2010 Issued
Array ( [id] => 8340034 [patent_doc_number] => 08241957 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Negative thermal expansion system (NTES) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging' [patent_app_type] => utility [patent_app_number] => 12/906690 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 8765 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906690 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906690
Negative thermal expansion system (NTES) device for TCE compensation in elastomer composites and conductive elastomer interconnects in microelectronic packaging Oct 17, 2010 Issued
Array ( [id] => 7784318 [patent_doc_number] => 20120045874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'CMOS INTEGRATION METHOD FOR OPTIMAL IO TRANSISTOR VT' [patent_app_type] => utility [patent_app_number] => 12/857954 [patent_app_country] => US [patent_app_date] => 2010-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3584 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045874.pdf [firstpage_image] =>[orig_patent_app_number] => 12857954 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857954
CMOS integration method for optimal IO transistor VT Aug 16, 2010 Issued
Array ( [id] => 7784297 [patent_doc_number] => 20120045853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-23 [patent_title] => 'SER Testing for an IC Chip Using Hot Underfill' [patent_app_type] => utility [patent_app_number] => 12/857864 [patent_app_country] => US [patent_app_date] => 2010-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20120045853.pdf [firstpage_image] =>[orig_patent_app_number] => 12857864 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/857864
SER testing for an IC chip using hot underfill Aug 16, 2010 Issued
Array ( [id] => 6024970 [patent_doc_number] => 20110053296 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'THIN FILM DEPOSITION APPARATUS AND METHOD OF MANUFACTURING ORGANIC LIGHT-EMITTING DISPLAY DEVICE BY USING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/856942 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 11926 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20110053296.pdf [firstpage_image] =>[orig_patent_app_number] => 12856942 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856942
Thin film deposition apparatus and method of manufacturing organic light-emitting display device by using the same Aug 15, 2010 Issued
Array ( [id] => 10876143 [patent_doc_number] => 08900927 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-12-02 [patent_title] => 'Multichip electronic packages and methods of manufacture' [patent_app_type] => utility [patent_app_number] => 12/856699 [patent_app_country] => US [patent_app_date] => 2010-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 14 [patent_no_of_words] => 3640 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12856699 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856699
Multichip electronic packages and methods of manufacture Aug 15, 2010 Issued
Array ( [id] => 7988753 [patent_doc_number] => 08076673 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-12-13 [patent_title] => 'Recessed gate dielectric antifuse' [patent_app_type] => utility [patent_app_number] => 12/856240 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4290 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/076/08076673.pdf [firstpage_image] =>[orig_patent_app_number] => 12856240 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856240
Recessed gate dielectric antifuse Aug 12, 2010 Issued
Array ( [id] => 6161825 [patent_doc_number] => 20110159639 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'Method for Making a Stackable Package' [patent_app_type] => utility [patent_app_number] => 12/856401 [patent_app_country] => US [patent_app_date] => 2010-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3498 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0159/20110159639.pdf [firstpage_image] =>[orig_patent_app_number] => 12856401 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/856401
Method for making a stackable package Aug 12, 2010 Issued
Array ( [id] => 6417063 [patent_doc_number] => 20100276749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-04 [patent_title] => 'VERTICAL TRANSISTORS' [patent_app_type] => utility [patent_app_number] => 12/836459 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 11405 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0276/20100276749.pdf [firstpage_image] =>[orig_patent_app_number] => 12836459 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/836459
Vertical transistors Jul 13, 2010 Issued
Array ( [id] => 7751534 [patent_doc_number] => 08110501 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-07 [patent_title] => 'Method of fabricating landing plug with varied doping concentration in semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/822461 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 3429 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 164 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/110/08110501.pdf [firstpage_image] =>[orig_patent_app_number] => 12822461 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822461
Method of fabricating landing plug with varied doping concentration in semiconductor device Jun 23, 2010 Issued
Array ( [id] => 6348441 [patent_doc_number] => 20100330773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/822304 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 9801 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0330/20100330773.pdf [firstpage_image] =>[orig_patent_app_number] => 12822304 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/822304
SUBSTRATE PROCESSING METHOD AND SUBSTRATE PROCESSING APPARATUS Jun 23, 2010 Abandoned
Array ( [id] => 9344945 [patent_doc_number] => 08664092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-04 [patent_title] => 'Method for cleaning silicon wafer, and method for producing epitaxial wafer using the cleaning method' [patent_app_type] => utility [patent_app_number] => 13/378065 [patent_app_country] => US [patent_app_date] => 2010-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4281 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13378065 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/378065
Method for cleaning silicon wafer, and method for producing epitaxial wafer using the cleaning method Jun 23, 2010 Issued
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