Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8139851 [patent_doc_number] => 20120094474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'METHOD FOR EQUIPPING AN EPITAXY REACTOR' [patent_app_type] => utility [patent_app_number] => 13/378340 [patent_app_country] => US [patent_app_date] => 2010-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1533 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0094/20120094474.pdf [firstpage_image] =>[orig_patent_app_number] => 13378340 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/378340
Method for equipping an epitaxy reactor Jun 7, 2010 Issued
Array ( [id] => 4608697 [patent_doc_number] => 07993952 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-08-09 [patent_title] => 'Charge transfer device' [patent_app_type] => utility [patent_app_number] => 12/772666 [patent_app_country] => US [patent_app_date] => 2010-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 33 [patent_no_of_words] => 4523 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/993/07993952.pdf [firstpage_image] =>[orig_patent_app_number] => 12772666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/772666
Charge transfer device May 2, 2010 Issued
Array ( [id] => 6493951 [patent_doc_number] => 20100200860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-12 [patent_title] => 'Thin Film Transistor Array Panel and Manufacturing Method Thereof' [patent_app_type] => utility [patent_app_number] => 12/763904 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 8089 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20100200860.pdf [firstpage_image] =>[orig_patent_app_number] => 12763904 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763904
Thin Film Transistor Array Panel and Manufacturing Method Thereof Apr 19, 2010 Abandoned
Array ( [id] => 6265588 [patent_doc_number] => 20100297854 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-11-25 [patent_title] => 'HIGH THROUGHPUT SELECTIVE OXIDATION OF SILICON AND POLYSILICON USING PLASMA AT ROOM TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 12/763653 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0297/20100297854.pdf [firstpage_image] =>[orig_patent_app_number] => 12763653 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763653
HIGH THROUGHPUT SELECTIVE OXIDATION OF SILICON AND POLYSILICON USING PLASMA AT ROOM TEMPERATURE Apr 19, 2010 Abandoned
Array ( [id] => 6235487 [patent_doc_number] => 20100267191 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-21 [patent_title] => 'PLASMA ENHANCED THERMAL EVAPORATOR' [patent_app_type] => utility [patent_app_number] => 12/763856 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7160 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0267/20100267191.pdf [firstpage_image] =>[orig_patent_app_number] => 12763856 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763856
PLASMA ENHANCED THERMAL EVAPORATOR Apr 19, 2010 Abandoned
Array ( [id] => 8858444 [patent_doc_number] => 08460979 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-11 [patent_title] => 'Method of fabricating a backside illuminated image sensor' [patent_app_type] => utility [patent_app_number] => 12/762442 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 2367 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12762442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762442
Method of fabricating a backside illuminated image sensor Apr 18, 2010 Issued
Array ( [id] => 6570063 [patent_doc_number] => 20100273310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'METHOD OF MANUFACTURING SOI SUBSTRATE' [patent_app_type] => utility [patent_app_number] => 12/762675 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9555 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0273/20100273310.pdf [firstpage_image] =>[orig_patent_app_number] => 12762675 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762675
Method of manufacturing SOI substrate Apr 18, 2010 Issued
Array ( [id] => 4533493 [patent_doc_number] => 07888193 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-15 [patent_title] => 'Semiconductor device with mushroom electrode and manufacture method thereof' [patent_app_type] => utility [patent_app_number] => 12/726761 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 44 [patent_no_of_words] => 8190 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/888/07888193.pdf [firstpage_image] =>[orig_patent_app_number] => 12726761 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726761
Semiconductor device with mushroom electrode and manufacture method thereof Mar 17, 2010 Issued
Array ( [id] => 6507527 [patent_doc_number] => 20100219469 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'MASK ROM CELL STRUCTURE AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/712400 [patent_app_country] => US [patent_app_date] => 2010-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4642 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0219/20100219469.pdf [firstpage_image] =>[orig_patent_app_number] => 12712400 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/712400
MASK ROM CELL STRUCTURE AND METHOD OF FABRICATING THE SAME Feb 24, 2010 Abandoned
Array ( [id] => 6540860 [patent_doc_number] => 20100221911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-02 [patent_title] => 'PROVIDING SUPERIOR ELECTROMIGRATION PERFORMANCE AND REDUCING DETERIORATION OF SENSITIVE LOW-K DIELECTRICS IN METALLIZATION SYSTEMS OF SEMICONDUCTOR DEVICES' [patent_app_type] => utility [patent_app_number] => 12/711373 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0221/20100221911.pdf [firstpage_image] =>[orig_patent_app_number] => 12711373 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711373
Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices Feb 23, 2010 Issued
Array ( [id] => 8329047 [patent_doc_number] => 08237146 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-07 [patent_title] => 'Memory cell with silicon-containing carbon switching layer and methods for forming the same' [patent_app_type] => utility [patent_app_number] => 12/711810 [patent_app_country] => US [patent_app_date] => 2010-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 9527 [patent_no_of_claims] => 55 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 39 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12711810 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/711810
Memory cell with silicon-containing carbon switching layer and methods for forming the same Feb 23, 2010 Issued
Array ( [id] => 6042366 [patent_doc_number] => 20110204443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'SEMICONDUCTOR-ON-INSULATOR (SOI) STRUCTURE AND METHOD OF FORMING THE SOI STRUCTURE USING A BULK SEMICONDUCTOR STARTING WAFER' [patent_app_type] => utility [patent_app_number] => 12/710380 [patent_app_country] => US [patent_app_date] => 2010-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 7469 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20110204443.pdf [firstpage_image] =>[orig_patent_app_number] => 12710380 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710380
Semiconductor-on-insulator (SOI) structure and method of forming the SOI structure using a bulk semiconductor starting wafer Feb 22, 2010 Issued
Array ( [id] => 8944393 [patent_doc_number] => 08497575 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-30 [patent_title] => 'Semiconductor packaging system with an aligned interconnect and method of manufacture thereof' [patent_app_type] => utility [patent_app_number] => 12/710359 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4393 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12710359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710359
Semiconductor packaging system with an aligned interconnect and method of manufacture thereof Feb 21, 2010 Issued
Array ( [id] => 6047728 [patent_doc_number] => 20110207274 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-08-25 [patent_title] => 'METHOD FOR FORMING A SPLIT-GATE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/710111 [patent_app_country] => US [patent_app_date] => 2010-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3212 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0207/20110207274.pdf [firstpage_image] =>[orig_patent_app_number] => 12710111 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/710111
Method for forming a split-gate memory cell Feb 21, 2010 Issued
Array ( [id] => 6264323 [patent_doc_number] => 20100252930 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-07 [patent_title] => 'Method for Improving Performance of Etch Stop Layer' [patent_app_type] => utility [patent_app_number] => 12/708160 [patent_app_country] => US [patent_app_date] => 2010-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2865 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0252/20100252930.pdf [firstpage_image] =>[orig_patent_app_number] => 12708160 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/708160
Method for Improving Performance of Etch Stop Layer Feb 17, 2010 Abandoned
Array ( [id] => 8294309 [patent_doc_number] => 08222093 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-17 [patent_title] => 'Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devices' [patent_app_type] => utility [patent_app_number] => 12/707150 [patent_app_country] => US [patent_app_date] => 2010-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 11 [patent_no_of_words] => 5698 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12707150 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/707150
Methods for forming barrier regions within regions of insulating material resulting in outgassing paths from the insulating material and related devices Feb 16, 2010 Issued
Array ( [id] => 8932563 [patent_doc_number] => 08492262 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-07-23 [patent_title] => 'Direct IMS (injection molded solder) without a mask for forming solder bumps on substrates' [patent_app_type] => utility [patent_app_number] => 12/706212 [patent_app_country] => US [patent_app_date] => 2010-02-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 54 [patent_no_of_words] => 6827 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12706212 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/706212
Direct IMS (injection molded solder) without a mask for forming solder bumps on substrates Feb 15, 2010 Issued
Array ( [id] => 7811251 [patent_doc_number] => 08133781 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-03-13 [patent_title] => 'Method of forming a buried plate by ion implantation' [patent_app_type] => utility [patent_app_number] => 12/705768 [patent_app_country] => US [patent_app_date] => 2010-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6342 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/133/08133781.pdf [firstpage_image] =>[orig_patent_app_number] => 12705768 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/705768
Method of forming a buried plate by ion implantation Feb 14, 2010 Issued
Array ( [id] => 7762096 [patent_doc_number] => 08114732 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Method for manufacturing twin bit structure cell with Al2O3/nano-crystalline Si layer' [patent_app_type] => utility [patent_app_number] => 12/704502 [patent_app_country] => US [patent_app_date] => 2010-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 3684 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/114/08114732.pdf [firstpage_image] =>[orig_patent_app_number] => 12704502 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/704502
Method for manufacturing twin bit structure cell with Al2O3/nano-crystalline Si layer Feb 10, 2010 Issued
Array ( [id] => 6501236 [patent_doc_number] => 20100210088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-08-19 [patent_title] => 'MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/703252 [patent_app_country] => US [patent_app_date] => 2010-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13593 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0210/20100210088.pdf [firstpage_image] =>[orig_patent_app_number] => 12703252 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/703252
Manufacturing method of semiconductor device Feb 9, 2010 Issued
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