Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7773780 [patent_doc_number] => 08119425 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-21 [patent_title] => 'Method of forming magnetic memory device' [patent_app_type] => utility [patent_app_number] => 12/655862 [patent_app_country] => US [patent_app_date] => 2010-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7508 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 161 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/119/08119425.pdf [firstpage_image] =>[orig_patent_app_number] => 12655862 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/655862
Method of forming magnetic memory device Jan 7, 2010 Issued
Array ( [id] => 6102256 [patent_doc_number] => 20110165749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-07 [patent_title] => 'METHOD OF MAKING A SEMICONDUCTOR STRUCTURE USEFUL IN MAKING A SPLIT GATE NON-VOLATILE MEMORY CELL' [patent_app_type] => utility [patent_app_number] => 12/683972 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3364 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0165/20110165749.pdf [firstpage_image] =>[orig_patent_app_number] => 12683972 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/683972
Method of making a semiconductor structure useful in making a split gate non-volatile memory cell Jan 6, 2010 Issued
Array ( [id] => 6398777 [patent_doc_number] => 20100178759 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'Method of fabricating semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/654881 [patent_app_country] => US [patent_app_date] => 2010-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20100178759.pdf [firstpage_image] =>[orig_patent_app_number] => 12654881 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/654881
Method of fabricating semiconductor device Jan 6, 2010 Issued
Array ( [id] => 6398795 [patent_doc_number] => 20100178763 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-15 [patent_title] => 'METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/651673 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6235 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0178/20100178763.pdf [firstpage_image] =>[orig_patent_app_number] => 12651673 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651673
METHOD AND APPARATUS FOR FABRICATING SEMICONDUCTOR DEVICE Jan 3, 2010 Abandoned
Array ( [id] => 8176989 [patent_doc_number] => 08178408 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-05-15 [patent_title] => 'Methods of manufacturing charge trap-type non-volatile memory devices' [patent_app_type] => utility [patent_app_number] => 12/651781 [patent_app_country] => US [patent_app_date] => 2010-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 3692 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/178/08178408.pdf [firstpage_image] =>[orig_patent_app_number] => 12651781 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/651781
Methods of manufacturing charge trap-type non-volatile memory devices Jan 3, 2010 Issued
Array ( [id] => 7519264 [patent_doc_number] => 07973367 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-07-05 [patent_title] => 'Semiconductor device and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 12/650009 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 34 [patent_no_of_words] => 17533 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/973/07973367.pdf [firstpage_image] =>[orig_patent_app_number] => 12650009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/650009
Semiconductor device and manufacturing method thereof Dec 29, 2009 Issued
Array ( [id] => 6448724 [patent_doc_number] => 20100105189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-29 [patent_title] => 'METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 12/649116 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5141 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0105/20100105189.pdf [firstpage_image] =>[orig_patent_app_number] => 12649116 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649116
METHOD OF FABRICATING SEMICONDUCTOR MEMORY DEVICE Dec 28, 2009 Abandoned
Array ( [id] => 7965863 [patent_doc_number] => 07939418 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-05-10 [patent_title] => 'Partial implantation method for semiconductor manufacturing' [patent_app_type] => utility [patent_app_number] => 12/646196 [patent_app_country] => US [patent_app_date] => 2009-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 23 [patent_no_of_words] => 8870 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/939/07939418.pdf [firstpage_image] =>[orig_patent_app_number] => 12646196 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/646196
Partial implantation method for semiconductor manufacturing Dec 22, 2009 Issued
Array ( [id] => 4547182 [patent_doc_number] => 07876438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-01-25 [patent_title] => 'Apparatus and methods for determining overlay and uses of same' [patent_app_type] => utility [patent_app_number] => 12/560229 [patent_app_country] => US [patent_app_date] => 2009-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 17 [patent_no_of_words] => 13941 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/876/07876438.pdf [firstpage_image] =>[orig_patent_app_number] => 12560229 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/560229
Apparatus and methods for determining overlay and uses of same Sep 14, 2009 Issued
Array ( [id] => 6025010 [patent_doc_number] => 20110053336 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/553261 [patent_app_country] => US [patent_app_date] => 2009-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 1857 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0053/20110053336.pdf [firstpage_image] =>[orig_patent_app_number] => 12553261 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/553261
METHOD FOR SELECTIVE DEPOSITION OF DIELECTRIC LAYERS ON SEMICONDUCTOR STRUCTURES Sep 2, 2009 Abandoned
Array ( [id] => 6597328 [patent_doc_number] => 20100062600 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-11 [patent_title] => 'Method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/585022 [patent_app_country] => US [patent_app_date] => 2009-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4487 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20100062600.pdf [firstpage_image] =>[orig_patent_app_number] => 12585022 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/585022
Method of manufacturing a semiconductor device Aug 31, 2009 Abandoned
Array ( [id] => 4431861 [patent_doc_number] => 07968401 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-28 [patent_title] => 'Reducing photoresist layer degradation in plasma immersion ion implantation' [patent_app_type] => utility [patent_app_number] => 12/550142 [patent_app_country] => US [patent_app_date] => 2009-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 4655 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/968/07968401.pdf [firstpage_image] =>[orig_patent_app_number] => 12550142 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/550142
Reducing photoresist layer degradation in plasma immersion ion implantation Aug 27, 2009 Issued
Array ( [id] => 4575294 [patent_doc_number] => 07859090 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-28 [patent_title] => 'Die attach method and leadframe structure' [patent_app_type] => utility [patent_app_number] => 12/549324 [patent_app_country] => US [patent_app_date] => 2009-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 13 [patent_no_of_words] => 4256 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/859/07859090.pdf [firstpage_image] =>[orig_patent_app_number] => 12549324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/549324
Die attach method and leadframe structure Aug 26, 2009 Issued
Array ( [id] => 44946 [patent_doc_number] => 07777222 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-17 [patent_title] => 'Nanotube device structure and methods of fabrication' [patent_app_type] => utility [patent_app_number] => 12/548131 [patent_app_country] => US [patent_app_date] => 2009-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 54 [patent_no_of_words] => 8726 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/777/07777222.pdf [firstpage_image] =>[orig_patent_app_number] => 12548131 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/548131
Nanotube device structure and methods of fabrication Aug 25, 2009 Issued
Array ( [id] => 4451190 [patent_doc_number] => 07964513 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Method to form ultra high quality silicon-containing compound layers' [patent_app_type] => utility [patent_app_number] => 12/546106 [patent_app_country] => US [patent_app_date] => 2009-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 19 [patent_no_of_words] => 13994 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/964/07964513.pdf [firstpage_image] =>[orig_patent_app_number] => 12546106 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/546106
Method to form ultra high quality silicon-containing compound layers Aug 23, 2009 Issued
Array ( [id] => 6070797 [patent_doc_number] => 20110045648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'METHODS FOR FABRICATING BULK FINFET DEVICES HAVING DEEP TRENCH ISOLATION' [patent_app_type] => utility [patent_app_number] => 12/544931 [patent_app_country] => US [patent_app_date] => 2009-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3502 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20110045648.pdf [firstpage_image] =>[orig_patent_app_number] => 12544931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/544931
Methods for fabricating bulk FinFET devices having deep trench isolation Aug 19, 2009 Issued
Array ( [id] => 7496779 [patent_doc_number] => 20110260219 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-10-27 [patent_title] => 'PROTECTIVE LAYERS SUITABLE FOR EXHAUST GASES FOR HIGH-TEMPERATURE CHEMFET EXHAUST GAS SENSORS' [patent_app_type] => utility [patent_app_number] => 12/998079 [patent_app_country] => US [patent_app_date] => 2009-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5185 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0260/20110260219.pdf [firstpage_image] =>[orig_patent_app_number] => 12998079 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/998079
PROTECTIVE LAYERS SUITABLE FOR EXHAUST GASES FOR HIGH-TEMPERATURE CHEMFET EXHAUST GAS SENSORS Jul 15, 2009 Abandoned
Array ( [id] => 5485385 [patent_doc_number] => 20090275150 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-11-05 [patent_title] => 'FILM FORMATION APPARATUS AND METHOD FOR SEMICONDUCTOR PROCESS' [patent_app_type] => utility [patent_app_number] => 12/504454 [patent_app_country] => US [patent_app_date] => 2009-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5253 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20090275150.pdf [firstpage_image] =>[orig_patent_app_number] => 12504454 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/504454
Film formation apparatus and method for semiconductor process Jul 15, 2009 Issued
Array ( [id] => 4485541 [patent_doc_number] => 07883919 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Negative thermal expansion system (NTEs) device for TCE compensation in elastomer compsites and conductive elastomer interconnects in microelectronic packaging' [patent_app_type] => utility [patent_app_number] => 12/497903 [patent_app_country] => US [patent_app_date] => 2009-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 31 [patent_no_of_words] => 8759 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/883/07883919.pdf [firstpage_image] =>[orig_patent_app_number] => 12497903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/497903
Negative thermal expansion system (NTEs) device for TCE compensation in elastomer compsites and conductive elastomer interconnects in microelectronic packaging Jul 5, 2009 Issued
Array ( [id] => 5404032 [patent_doc_number] => 20090239346 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'SEMICONDUCTOR DEVICE WITH FINFET AND METHOD OF FABRICATING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/477348 [patent_app_country] => US [patent_app_date] => 2009-06-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6335 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20090239346.pdf [firstpage_image] =>[orig_patent_app_number] => 12477348 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/477348
Semiconductor device with FinFET and method of fabricating the same Jun 2, 2009 Issued
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