Search

Scott R. Wilson

Examiner (ID: 11542, Phone: (571)272-1925 , Office: P/2826 )

Most Active Art Unit
2826
Art Unit(s)
2826
Total Applications
901
Issued Applications
779
Pending Applications
16
Abandoned Applications
106

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8421648 [patent_doc_number] => 08278136 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-02 [patent_title] => 'Semiconductor device, method for producing the same, sensor and electro-optical device' [patent_app_type] => utility [patent_app_number] => 12/474931 [patent_app_country] => US [patent_app_date] => 2009-05-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 24 [patent_no_of_words] => 10691 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 213 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12474931 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/474931
Semiconductor device, method for producing the same, sensor and electro-optical device May 28, 2009 Issued
Array ( [id] => 6119649 [patent_doc_number] => 20110076790 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'METHOD FOR CONTROLLING THRESHOLD VOLTAGE OF SEMICONDUCTOR ELEMENT' [patent_app_type] => utility [patent_app_number] => 12/992073 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 13400 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0076/20110076790.pdf [firstpage_image] =>[orig_patent_app_number] => 12992073 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/992073
Method for controlling threshold voltage of semiconductor element May 10, 2009 Issued
Array ( [id] => 6114584 [patent_doc_number] => 20110074013 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-31 [patent_title] => 'FILM FORMING METHOD OF SILICON OXIDE FILM, SILICON OXIDE FILM, SEMICONDUCTOR DEVICE, AND MANUFACTURING METHOD OF SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/992209 [patent_app_country] => US [patent_app_date] => 2009-05-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 12043 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20110074013.pdf [firstpage_image] =>[orig_patent_app_number] => 12992209 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/992209
Film forming method of silicon oxide film, silicon oxide film, semiconductor device, and manufacturing method of semiconductor device May 10, 2009 Issued
Array ( [id] => 5404006 [patent_doc_number] => 20090239320 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-24 [patent_title] => 'SEMICONDUCTOR DEVICE AND PEELING OFF METHOD AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/432906 [patent_app_country] => US [patent_app_date] => 2009-04-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 25023 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0239/20090239320.pdf [firstpage_image] =>[orig_patent_app_number] => 12432906 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/432906
Semiconductor device and peeling off method and method of manufacturing semiconductor device Apr 29, 2009 Issued
Array ( [id] => 5480215 [patent_doc_number] => 20090203172 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'Enhanced Die-Up Ball Grid Array and Method for Making the Same' [patent_app_type] => utility [patent_app_number] => 12/424270 [patent_app_country] => US [patent_app_date] => 2009-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 11608 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20090203172.pdf [firstpage_image] =>[orig_patent_app_number] => 12424270 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/424270
Enhanced Die-Up Ball Grid Array and Method for Making the Same Apr 14, 2009 Abandoned
Array ( [id] => 53783 [patent_doc_number] => 07767531 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-03 [patent_title] => 'Method of forming transistor having channel region at sidewall of channel portion hole' [patent_app_type] => utility [patent_app_number] => 12/418359 [patent_app_country] => US [patent_app_date] => 2009-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 7625 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/767/07767531.pdf [firstpage_image] =>[orig_patent_app_number] => 12418359 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/418359
Method of forming transistor having channel region at sidewall of channel portion hole Apr 2, 2009 Issued
Array ( [id] => 5383081 [patent_doc_number] => 20090224325 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-09-10 [patent_title] => 'ANTIFUSE ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/413078 [patent_app_country] => US [patent_app_date] => 2009-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6702 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0224/20090224325.pdf [firstpage_image] =>[orig_patent_app_number] => 12413078 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/413078
Antifuse elements Mar 26, 2009 Issued
Array ( [id] => 6070773 [patent_doc_number] => 20110045624 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'PHOSPHORUS PASTE FOR DIFFUSION AND PROCESS FOR PRODUCING SOLAR BATTERY UTILIZING THE PHOSPHORUS PASTE' [patent_app_type] => utility [patent_app_number] => 12/933738 [patent_app_country] => US [patent_app_date] => 2009-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 8767 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0045/20110045624.pdf [firstpage_image] =>[orig_patent_app_number] => 12933738 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/933738
Phosphorus paste for diffusion and process for producing solar battery utilizing the phosphorus paste Mar 17, 2009 Issued
Array ( [id] => 5477590 [patent_doc_number] => 20090200547 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-08-13 [patent_title] => 'TRENCH DEPTH MONITOR FOR SEMICONDUCTOR MANUFACTURING' [patent_app_type] => utility [patent_app_number] => 12/371021 [patent_app_country] => US [patent_app_date] => 2009-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3458 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0200/20090200547.pdf [firstpage_image] =>[orig_patent_app_number] => 12371021 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/371021
Trench depth monitor for semiconductor manufacturing Feb 12, 2009 Issued
Array ( [id] => 5419692 [patent_doc_number] => 20090146146 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'Semiconductor Device formed in a Recrystallized Layer' [patent_app_type] => utility [patent_app_number] => 12/368122 [patent_app_country] => US [patent_app_date] => 2009-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4405 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20090146146.pdf [firstpage_image] =>[orig_patent_app_number] => 12368122 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/368122
Semiconductor device formed in a recrystallized layer Feb 8, 2009 Issued
Array ( [id] => 5275455 [patent_doc_number] => 20090127587 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'TUNABLE ANTIFUSE ELEMENTS' [patent_app_type] => utility [patent_app_number] => 12/361944 [patent_app_country] => US [patent_app_date] => 2009-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5125 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0127/20090127587.pdf [firstpage_image] =>[orig_patent_app_number] => 12361944 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/361944
Tunable antifuse elements Jan 28, 2009 Issued
Array ( [id] => 9375599 [patent_doc_number] => 08679862 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-03-25 [patent_title] => 'Method and device for manufacturing thin film photoelectric conversion module' [patent_app_type] => utility [patent_app_number] => 12/867585 [patent_app_country] => US [patent_app_date] => 2009-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 7324 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12867585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/867585
Method and device for manufacturing thin film photoelectric conversion module Jan 27, 2009 Issued
Array ( [id] => 4614202 [patent_doc_number] => 07989883 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird\'s beak structure in the manufacture of a semiconductor device' [patent_app_type] => utility [patent_app_number] => 12/321205 [patent_app_country] => US [patent_app_date] => 2009-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 11 [patent_no_of_words] => 2167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/989/07989883.pdf [firstpage_image] =>[orig_patent_app_number] => 12321205 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/321205
System and method for providing a poly cap and a no field oxide area to prevent formation of a vertical bird's beak structure in the manufacture of a semiconductor device Jan 15, 2009 Issued
Array ( [id] => 54048 [patent_doc_number] => 07772633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-08-10 [patent_title] => 'DRAM cells with vertical transistors' [patent_app_type] => utility [patent_app_number] => 12/339610 [patent_app_country] => US [patent_app_date] => 2008-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 35 [patent_no_of_words] => 11361 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/772/07772633.pdf [firstpage_image] =>[orig_patent_app_number] => 12339610 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/339610
DRAM cells with vertical transistors Dec 18, 2008 Issued
Array ( [id] => 6397546 [patent_doc_number] => 20100304575 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-02 [patent_title] => 'METHOD AND ARRANGEMENT FOR TEMPERING SIC WAFERS' [patent_app_type] => utility [patent_app_number] => 12/747283 [patent_app_country] => US [patent_app_date] => 2008-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 1741 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0304/20100304575.pdf [firstpage_image] =>[orig_patent_app_number] => 12747283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/747283
METHOD AND ARRANGEMENT FOR TEMPERING SIC WAFERS Dec 9, 2008 Abandoned
Array ( [id] => 6220833 [patent_doc_number] => 20100055815 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'METHOD OF MANFUACTURING LENS FOR LIGHT EMITTING DIODE PACKAGE' [patent_app_type] => utility [patent_app_number] => 12/246591 [patent_app_country] => US [patent_app_date] => 2008-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2052 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20100055815.pdf [firstpage_image] =>[orig_patent_app_number] => 12246591 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/246591
METHOD OF MANFUACTURING LENS FOR LIGHT EMITTING DIODE PACKAGE Oct 6, 2008 Abandoned
Array ( [id] => 5278729 [patent_doc_number] => 20090130861 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-05-21 [patent_title] => 'DUAL DAMASCENE INTEGRATION STRUCTURES AND METHOD OF FORMING IMPROVED DUAL DAMASCENE INTEGRATION STRUCTURES' [patent_app_type] => utility [patent_app_number] => 12/246352 [patent_app_country] => US [patent_app_date] => 2008-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6887 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0130/20090130861.pdf [firstpage_image] =>[orig_patent_app_number] => 12246352 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/246352
DUAL DAMASCENE INTEGRATION STRUCTURES AND METHOD OF FORMING IMPROVED DUAL DAMASCENE INTEGRATION STRUCTURES Oct 5, 2008 Abandoned
Array ( [id] => 6221012 [patent_doc_number] => 20100055898 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-03-04 [patent_title] => 'METHOD FOR FABRICATING AN INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/246451 [patent_app_country] => US [patent_app_date] => 2008-10-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 1746 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20100055898.pdf [firstpage_image] =>[orig_patent_app_number] => 12246451 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/246451
METHOD FOR FABRICATING AN INTEGRATED CIRCUIT Oct 5, 2008 Abandoned
Array ( [id] => 6356808 [patent_doc_number] => 20100087036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'MODULE HAVING A STACKED PASSIVE ELEMENT AND METHOD OF FORMING THE SAME' [patent_app_type] => utility [patent_app_number] => 12/244672 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4933 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0087/20100087036.pdf [firstpage_image] =>[orig_patent_app_number] => 12244672 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244672
Module having a stacked passive element and method of forming the same Oct 1, 2008 Issued
Array ( [id] => 4492703 [patent_doc_number] => 07955914 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-07 [patent_title] => 'Method of producing an asymmetric architecture semi-conductor device' [patent_app_type] => utility [patent_app_number] => 12/244051 [patent_app_country] => US [patent_app_date] => 2008-10-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 17 [patent_no_of_words] => 6150 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/955/07955914.pdf [firstpage_image] =>[orig_patent_app_number] => 12244051 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/244051
Method of producing an asymmetric architecture semi-conductor device Oct 1, 2008 Issued
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